f25l32qa Elite Semiconductor Memory Technology Inc., f25l32qa Datasheet - Page 19
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f25l32qa
Manufacturer Part Number
f25l32qa
Description
3v Only 32 Mbit Serial Flash Memory With Dual And Quad
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
1.F25L32QA.pdf
(42 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
f25l32qa-100PAG
Manufacturer:
EMST
Quantity:
20 000
ESMT
Fast Read Quad I/O (50 MHz ~ 100 MHz)
The Fast Read Quad I/O (EBH) instruction is similar to the Fast
Read Quad Output (6BH) instruction, but with the capability to
input address bits [A
(QE) bit of Status Register-2 must be set “1” to enable Quad
function.
To set mode bits [M
further reduce instruction overhead (See Figure 8). The upper
mode bits [M
I/O instruction with/without the first byte command code (EBH).
The lower mode bits [M
Elite Semiconductor Memory Technology Inc.
Figure 8: Fast Read Quad I/O Sequence ([M
Figure 9: Fast Read Quad I/O Sequence ([M
7
–M
4
] controls the length of next Fast Read Quad
23
7
-M
3
-A
–M
SCK
SIO
SIO
SIO
SIO
0
CE
0
] after the address bits [A
Note: The mode bits [M3 -M0] are “don’t care”.
] four bits per clock. A Quad Enable
0
0
1
2
3
] are “don’t care”.
SCK
SIO
SIO
SIO
CE
SIO
Note: The mode bits [M3 -M0] are “don’t care”.
MODE0
MODE3
However , the IO pins sh ould be high-impe fance piror to the fall ing edge of the fi rst data clock.
0
1
2
3
MODE0
MODE3
However , the IO pins sh ould be high-imp efance piror to the falling edge of the fi rst data clock.
HIGH IMPE NANCE
HIGH IMPENANCE
HIGH IMP ENANCE
MSB
0 1 2 3 4 5 6 7 8
20 16 12 8
21 1 7
22 18
23 19
0 1 2 3
EB
13 9
14 10 6
15 11 7
7
7
A
-M
-M
23-0
(Preliminary)
0
0
4
5
] = 0xH or NOT AxH)
4 5 6 7 8
] = AxH)
23
0
1
2
3
-A
20 16 12 8
21 17
22 18
23 19
4
5
6
7
M
0
7-0
] can
0
1
2
3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
13 9
14 10 6
15 11
Dummy
A
9 10 11 12 13 14 15 16
23- 0
4
5
7
0
1 5
2 6
3 7
If [M
(See Figure 9). This way let the instruction sequence reduce 8
clocks and allows to enter address immediately after CE is
asserted low. If [M
instruction need the first byte command code, thus returning to
normal operation. A Mode Bit Reset (FFH) also can be used to
reset mode bits [M
CE is raised and the lowered) doesn’t need the command code
4 0 4 0
5 1 5 1 5 1
6 2 6 2 6 2
7 3 7 3 7 3
D
4 0
M
N
OUT
7 -0
1
2
3
7
D
N+1
–M
Dummy
OUT
IO
0
0
] = “AxH”, the next Fast Read Quad I/O instruction (after
4 0
switches from Input to Oup ut
N+2
D
OU T
4 0 4 0
5 1 5 1 5 1
6 2 6 2 6 2
7 3 7 3 7 3
D
N
OUT
7
7
D
N+1
–M
–M
OUT
IO
0
4 0
0
0
switches from Input to Ouput
] are the value other than “AxH”, the next
N+2
D
] before issuing normal instructions.
OUT
Publication Date: Jan. 2009
Revision: 0.2
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