f25l32qa Elite Semiconductor Memory Technology Inc., f25l32qa Datasheet - Page 9

• Manufacturer Part Number: f25l32qa
• Description: 3v Only 32 Mbit Serial Flash Memory With Dual And Quad
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
• Power-up
• Write Disable (WRDI) instruction completion
• Page Program instruction completion
• Auto Address Increment (AAI) Programming is completed and
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
• Write Status Register instructions
Elite Semiconductor Memory Technology Inc.
STATUS REGISTER
reached its highest unprotected memory address
Note:
Status Register - 1
Status Register - 2
10~15
Bit
0
1
2
3
4
5
6
7
8
9
1. Only BP0, BP1, BP2, BPL and QE are writable.
2. All register bits are volatility
3. All area are protected at power-on (BP2=BP1=BP0=1)
RESERVED
RESERVED
RESERVED
BUSY
Name
WEL
BP0
BP1
BP2
BPL
AAI
QE
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Reserved for future use
Auto Address Increment Programming status
1 = AAI programming mode
0 = Page Program mode
1 = BP2,BP1,BP0 are read-only bits
0 = BP2,BP1,BP0 are read/writable
Reserved for future use
1 = Quad enabled
0 = Quad disabled
Reserved for future use
Table 2: Software Status Register
(Preliminary)
Function
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
BUSY
The BUSY bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the BUSY bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Auto Address Increment (AAI)
The Auto-Address-Increment-Programming-Status bit provides
status on whether the device is in AAI Programming mode or
Page Program mode. The default at power up is Page Program
mode.
Publication Date: Jan. 2009
Revision: 0.2
Default at
Power-up
0
0
0
0
0
0
1
1
1
0
0
F25L32QA
Read/Write
R/W
R/W
R/W
R/W
R/W
N/A
N/A
N/A
R
R
R
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