as7c33128pfs32a Alliance Memory, Inc, as7c33128pfs32a Datasheet - Page 11

• Manufacturer Part Number: as7c33128pfs32a
• Description: 3.3v 128k X 32/36 Pipeline Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

AC test conditions
Notes
1
2
3
4
5
6
7
8
Package Dimensions
100-pin quad flat pack (TQFP)
3/4/02; v.1.4
+3.0V
• Output load: see Figure B, except for t
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to
Chip select refers to
HZOE
GND
Figure A: Input waveform
10%
is less than t
90%
Dimensions in millimeters
Hd
A1
A2
He
L1
D
b
E
L
c
e
GWE, BWE, BW[a:d]
LZOE
CE0, CE1, CE2.
; and t
Min
13.90
19.90
15.90
21.90
0.05
1.35
0.22
0.09
0.45
0°
0.65 nominal
1.00 nominal
TQFP
90%
HZC
10%
is less than t
.
Max
14.10
20.10
16.10
22.10
0.15
1.45
0.38
0.20
0.75
7°
D
OUT
LZC
LZC
at any given temperature and voltage.
, t
Figure B: Output load (A)
LZOE
Alliance Semiconductor
Z
c
0
, t
= 50
HZOE
L1
L
, t
HZC
He E
, see Figure C.
50
30 pF*
V
L
for 3.3V I/O;
= V
for 2.5V I/O
®
= 1.5V
DDQ
/2
Hd
353
D
D
OUT
Figure C: Output load (B)
A1 A2
AS7C33128PFS32A
AS7C33128PFS36A
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319
5 pF*
GND
*including scope
and jig capacitance
e
b
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