as7c33256ft32a Alliance Memory, Inc, as7c33256ft32a Datasheet
as7c33256ft32a
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as7c33256ft32a Summary of contents
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... Byte write registers CLK D Q Enable CE register CLK CLK D Q Enable Power delay down register CLK -75 8.5 7.5 300 110 30 Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A 256K × 32/36 Memory array 32/36 32/ Output Input registers registers CLK 32/36 DQ[a:d] -85 -10 Units 10 12 8.5 10 275 250 100 Copyright © ...
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... PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...
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... SSQ V 27 DDQ DQP / 11/30/04, v 1.1 ® TQFP 14 × Note: Pins 1, 30, 51, 80 are NC for ×32 Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A DQP / DDQ V 76 SSQ ...
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... WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). • Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C33256FT32A and AS7C33256FT36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP. ...
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... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. PUS 11/30/04, v 1.1 ® Description or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ is SB2 ZZI Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A . The duration of SB2 ...
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... Address Address Address Address Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A ...
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... Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A CLK Operation Deselect Deselect Deselect Deselect Deselect External Begin read External Begin read ...
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... Symbol Min Nominal V 3.135 3 3.135 3.3 DDQ Vss 0 0 Symbol Min Nominal V 3.135 3 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A Min Max Unit –0.5 +4.6 –0 0.5 DD –0 0.5 DDQ – 1.8 – –65 +150 –65 +135 Max Unit 3.465 V 3.465 ...
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... All V – 0.2V, Deselected < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all ≥ V Deselected Max ≤ ≥ V all Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A Min Max Unit -2 2 µA DD < µA DDQ 2 2** V +0.3 DDQ -0 ...
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... ADSPS t 2.0 – 2.0 ADSCS t 0.5 – 0.5 ADVH t 0.5 – 0.5 ADSPH t 0.5 – 0.5 ADSCH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A –10 Min Max Unit Notes – 12 – ns 8.5 – 4.0 – 4.0 ns – 2.5 – ns 2,3,4 – 2.5 – ns – 0 – ns 2,3,4 4.0 – 4.0 ns 2,3,4 5.0 – ...
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... ADV inserts wait states t HZOE t OH Q(A2Ý01) Q(A2Ý10) Q(A2Ý11 Read Burst Burst Suspend Burst Q(A2) Read Read Read Read Q(A 2Ý01 ) Q(A 2Ý10 ) Q(A 2Ý10 ) Q(A 2Ý11 ) Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A A3 Q(A3) Q(A3Ý01) Q(A3Ý11) Q(A3Ý10) t HZC Read Burst Burst Burst Q(A3) Read Read Read DSEL Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý11 ) Undefined ...
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... CYC t CL ADSC LOADS NEW ADDRESS A2 ADV SUSPENDS BURST D(A2) D(A2Ý01) D(A2Ý01) Read Suspend ADV Suspend Write Q(A2) Write Burst Write D D(A 2Ý01 ) D(A1) Write D(A 2Ý01 ) Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A t ADSCS t ADSCH ADVS t ADVH D(A2Ý10) D(A2Ý11) D(A3) D(A3Ý01) D(A3Ý10) ADV ADV ...
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... ADVS t ADVH D(A2 HZOE LZOE Q(A3) Suspend Read Suspend Read Read Q(A2) Write Q(A3) Q(A1) D Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A t OH Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) ADV ADV ADV Suspend Burst Burst Burst Read Read Read Read Q(A 3Ý11 ) Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...
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... Din READ READ Q(A1) Q(A2) Note: ADV is don’t care here. 11/30/04, v 1.1 ® t CYC HZOE Q(A3) Q(A4 D(A5) D(A6) D(A7) READ WRITE READ WRITE Q(A3) D(A6) Q(A4) D(A5) Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A A10 Q(A9) Q(A10) D(A8) READ WRITE WRITE READ Q(A10) D(A7) D(A8) Q(A9 ...
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... OE t LZOE Din Dout Q(A1) t PDS ZZ ZZ Setup Cycle t ZZI I supply READ READ Q(A1) Q(A1Ý01) 11/30/04, v 1.1 ® HZC t PUS ZZ Recovery Cycle t RZZI I SB2 Sleep State Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A t CYC HZOE Q(A2) Q(A2(Ý01)) Normal Operation Mode READ READ Q(A2) Q(A2Ý01 ...
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... L OUT for 3.3V I/ DDQ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC is measured as low if below VIL. CL Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω D OUT 5 pF* 353Ω/1538Ω /2 GND *including scope and jig capacitance ...
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... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 11/30/04, v 1.1 ® Alliance Semiconductor AS7C33256FT32A AS7C33256FT36A α ...
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... Ordering information Package & Width AS7C33256FT32A-75TQC TQFP x32 AS7C33256FT32A-75TQI AS7C33256FT36A-75TQC TQFP x36 AS7C33256FT36A-75TQI Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C33256FT32A-85TQCN) Part numbering guide AS7C 33 256 1.Alliance Semiconductor SRAM prefix 2.Operating voltage 3.3V 3.Organization: 256 = 256K 4.Flow-through mode 5.Organization ...
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... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C33256FT32A AS7C33256FT36A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C33256FT32A AS7C33256FT36A Document Version: v 1.1 ...