as7c3364ntd32b Alliance Memory, Inc, as7c3364ntd32b Datasheet
as7c3364ntd32b
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as7c3364ntd32b Summary of contents
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... R/W Control BWa logic BWb BWc BWd LBO CLK ZZ 32/36 32/36 Data ] Q D Input Register CLK CLK CEN OE -200 5 200 3.0 375 135 30 Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B CLK 128K x 32/36 SRAM Array 32/36 32/36 32/36 CLK Output Register OE 32/36 DQ [a:d] -166 -133 Units 6 7.5 166 133 MHz 3.5 4 350 325 ...
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... PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B Speed 3 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.0/10 ns 7.5/8.0/10 ns 7.5/8.0/ ...
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... DDQ 21 V SSQ 22 DQd2 23 DQd3 24 DQd4 25 DQd5 26 V SSQ 27 V DDQ 28 DQd6 29 DQd7 30 DQPd/NC 4/28/05; v.1.3 ® TQFP 14x20mm Note: Pins 1,30,51,80 are NC for x32 Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B 80 DQPb/NC 79 DQb7 78 DQb6 77 V DDQ 76 V SSQ 75 DQb5 74 DQb4 73 DQb3 72 DQb2 71 V SSQ 70 V DDQ 69 ...
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... R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C3364NTD36B and AS7C3364NTD32B operate with a 3.3V ± 5% power supply for the device core (V circuits use a separate power supply (V 14× ...
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... Starting Address First increment Second increment Third increment Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B . The duration of SNOOZE SB2 Linear burst order (LBO = ...
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... External NOP/WRITE ABORT (Begin Burst) High Next Current Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B Operation DESELECT Cycle DESELECT Cycle DESELECT Cycle CONTINUE DESELECT Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) DUMMY READ (Continue Burst) WRITE CYCLE (Begin Burst) ...
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... Symbol Min Nominal V 3.135 3 3.135 3.3 DDQ Vss 0 0 Symbol Min Nominal V 3.135 3 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B Burst Dsel Burst Burst Min Max Unit –0.5 +4.6 V –0 0 –0 0.5 V DDQ – 1.8 W – –65 +150 o – ...
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... ZZ < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all V – 0. ≥ V Deselected – 0.2V, Max DD ≤ ≥ V all Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B Min Max Unit -2 2 µA < µA DDQ +0.3 DDQ -0.3** ...
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... ADVS t 0.4 – 0 0.4 – 0 0.4 – 0 0.4 – 0.5 - ADVH t 0.4 – 0.5 - CENH t 0.4 – 0.5 - CSH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B -133 1 Min Max Unit Notes - 133 MHz 2,3,4 1 2,3,4 - 4.0 ns 2,3,4 - 4.0 ns 2,3 ...
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... Falling input HZOE OE Q(A1) Q(A2) Q(A2Y‘01) Read Continue Continue Continue Q(A2) Read Read Read Q(A2Y‘10) Q(A2Y‘01) Q(A2Y‘11) Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B Undefined t CYC A3 t HLZC Q(A2Y‘10) Q(A3) Q(A2Y‘11) Continue Inhibit Read Read Clock Q(A3) Q(A3Y‘01 ...
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... Dout Q(n-2) Q(n-1) Write DSEL D(A1) 4/28/05; v.1.3 ® D(A1) D(A2) D(A2Y‘01) Write Continue Continue Continue D(A2) Write Write Write D(A2Y‘10) D(A2Y‘01) D(A2Y‘11) Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B t CYC D(A3) D(A2Y‘10) D(A2Y‘11) Continue Inhibit Write Write Clock D(A3) D(A3Y‘01 ...
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... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. 4/28/05; v.1.3 ® LZC OH D(A1) D(A2) Q(A3) D(A2Ý01) t HZOE Burst Read Burst Read Write Q(A3) Read Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B t CYC HZC Q(A4) D(A5) Q(A6) Q(A4Ý01) t LZOE DSEL Write Read Write D(A5) Q(A6) D(A7 ...
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... Command Read Burst Q(A1) Q(A1Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. 4/28/05; v.1.3 ® A2 Q(A1Ý01) Q(A1) Q(A1Ý10) STALL DSEL Burst Burst Q(A1Ý10) DSEL Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B A3 D(A2) Burst Write Write Burst NOP NOP D(A2) D(A2Ý10) D(A2Ý01) D(A3 ...
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... Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 4/28/05; v.1.3 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only High-Z Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B Normal operation Cycle ...
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... CLK. All other synchronous at any given temper- LZC inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω / 1667Ω ...
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... Package Dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.90 16.10 He 21.90 22.10 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 4/28/05; v.1.3 ® Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B b e α ...
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... TQFP ×32 AS7C3364NTD32B-200TQC TQFP ×36 AS7C3364NTD36B-200TQC TQFP ×32 AS7C3364NTD32B-200TQI TQFP ×36 AS7C3364NTD36B-200TQI Note: Add suffix ‘N’ to the above part number for lead free parts (Ex. AS7C3364NTD32B-166TQCN) Part numbering guide AS7C 1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33=3.3V 3.Organization: 64= 4.NTD =No Turn-around Delay, Pipelined mode. 5.Organization: 32=x32 ...
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... Revision History Rev. No. v.1.3 4/28/05; v.1.3 ® History Initial version Alliance Semiconductor AS7C3364NTD32B AS7C3364NTD36B Revised Date 4/28/ ...
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... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C3364NTD32B AS7C3364NTD36B ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C3364NTD32B / AS7C3364NTD36B Document Version: v.1.3 ...