as7c251mntf36a Alliance Memory, Inc, as7c251mntf36a Datasheet

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as7c251mntf36a

Manufacturer Part Number
as7c251mntf36a
Description
Manufacturer
Alliance Memory, Inc
Datasheet
January 2005
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
Logic block diagram
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
1/17/05, v 1.2
A[19:0]
ADSC
ADSP
GWE
CLK
BWE
ADV
2.5V 1M × 32/36 Flow-through synchronous SRAM
BW
BW
BW
BW
CE0
CE1
CE2
OE
ZZ
a
d
c
b
Power
down
Alliance Semiconductor
20
D
D
CE
CLK
CLK
D
CLK
D
CLK
D
CLK
D
CE
CLK
D
CLK
CLK
CE
CLR
Byte write
Byte write
Byte write
Byte write
registers
registers
registers
registers
register
325
130
Enable
-75
8.5
7.5
Address
register
register
delay
90
Enable
DQ
DQ
DQ
DQ
d
c
b
a
Q
Burst logic
Q
Q
Q
Q
Q
Q
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
LBO
Q0
Q1
20
®
2
18
20
2
CLK
OE
32/36
registers
300
130
-85
Output
8.5
10
90
4
1M × 32/36
Memory
DQ[a:d]
array
32/36
32/36
CLK
registers
Input
Copyright © Alliance Semiconductor. All rights reserved.
AS7C251MFT32A
AS7C251MFT36A
275
130
-10
10
12
90
1 of 19
Units
mA
mA
mA
ns
ns

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as7c251mntf36a Summary of contents

Page 1

January 2005 2.5V 1M × 32/36 Flow-through synchronous SRAM Features • Organization: 1,048,576 words × bits • Fast clock to data access: 7.5/8.5/10 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous flow-through operation • ...

Page 2

... AS7C252MNTD18A 1MX32 AS7C251MNTD32A 1MX36 AS7C251MNTD36A 2MX18 AS7C252MNTF18A 1MX32 AS7C251MNTF32A 1MX36 AS7C251MNTF36A 1 Core Power Supply: VDD = 2.5V + 0.125V 2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect FT : Flow-through Burst Synchronous SRAM ...

Page 3

Pin assignment 100-pin TQFP - top view NC/DQPc 1 DQc0 2 DQc1 DDQ V 5 SSQ 6 DQc2 DQc3 7 DQc4 8 DQc5 SSQ V 11 DDQ 12 DQc6 DQc7 ...

Page 4

Functional description The AS7C251MFT32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words × bits. Fast cycle times of 8.5/10/12 ns with clock access times (t Burst operation is initiated ...

Page 5

Signal descriptions Pin I/O Properties CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. DQ[a,b,c,d] ...

Page 6

Write enable truth table (per byte) Function GWE BWE L Write All Bytes H H Write Byte a H Write Byte c and d H Read H Key don’t care low high ...

Page 7

Synchronous truth table 1 CE0 CE1 CE2 ADSP ADSC ...

Page 8

Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature Temperature under bias Stresses greater than those listed ...

Page 9

DC electrical characteristics Parameter Sym † Input leakage current |I Output leakage current |I Input high (logic 1) voltage V Input low (logic 0) voltage V Output high voltage V Output low voltage V † LBO and ZZ pins have ...

Page 10

Timing characteristics over operating range Parameter Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data output invalid from clock high Output enable low to output low Z Output enable high to ...

Page 11

Key to switching waveforms Rising input Timing waveform of read cycle CLK t t ADSPS ADSPH ADSP t ADSCS ADSC Address GWE, BWE t t CSS CSH CE0, CE2 CE1 ...

Page 12

Timing waveform of write cycle t CH CLK t ADSPS t ADSPH ADSP ADSC Address BWE BW[a:d] t CSS t CSH CE0, CE2 CE1 ADV OE Din D(A1) Read Suspend Q(A1) Note: Ý = XOR ...

Page 13

Timing waveform of read/write cycle (ADSP Controlled; ADSC High) CLK t ADSPS t ADSPH ADSP Address A1 BWE BW[a:d] CE0, CE2 CE1 ADV OE Din LZC Dout Q(A1) Read Q(A1) Note: Ý = XOR when LBO = ...

Page 14

Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH) CLK t t ADSCS ADSCH ADSC ADDRESS BWE BW[a: CSS CSH CE0,CE2 CE1 LZOE Q(A1) Q(A2) Dout Din READ READ Q(A1) Q(A2) ...

Page 15

Timing waveform of power down cycle CLK t t ADSPS ADSPS ADSP ADSC A1 ADDRESS BWE BW[a: CSS CSH CE0,CE2 CE1 ADV LZOE Din Dout Q(A1) t PDS ZZ ZZ Setup Cycle t ZZI ...

Page 16

AC test conditions • Output load: For LZC LZOE HZOE • Input pulse level: GND to 2.5V. See Figure A. • Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure ...

Page 17

Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 ...

Page 18

Ordering information Package & Width AS7C251MFT32A-75TQC TQFP x32 AS7C251MFT32A-75TQI AS7C251MFT36A-75TQC TQFP x36 AS7C251MFT36A-75TQI Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C251MFT32A-85TQCN) Part numbering guide AS7C 1.Alliance Semiconductor SRAM ...

Page 19

Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt ...

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