as7c256b Alliance Memory, Inc, as7c256b Datasheet

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as7c256b

Manufacturer Part Number
as7c256b
Description
5v 32k X 8 Cmos Sram Common I/o
Manufacturer
Alliance Memory, Inc
Datasheet
12/5/06; V.1.0
Logic block diagram
Features
• Industrial (-40
• Organization: 32,768 words × 8 bits
• High speed
• Low power consumption via chip deselect
• One chip select plus one Output Enable pin
• Bidirectional data inputs and outputs
• TTL-compatible
GND
- 12 ns address access time
- 6 ns output enable access time
September 2006
Advance Information
V
A7
A0
A1
A2
A3
A4
A5
A6
CC
o
A
8
to 85
A
9
Address decoder
Input buffer
32,768 X 8
10
(262,144)
A
o
Array
11
C) temperature
A
12
A
13
A
14
A
5V 32K X 8 CMOS SRAM (Common I/O)
Control
circuit
Alliance Memory
WE
OE
CE
I/O7
I/O0
Pin arrangement
• 28-pin JEDEC standard packages
• ESD protection ≥ 2000 volts
- 300 mil SOJ
- 8 × 13.4 mm TSOP
- 300 mil PDIP
28-pin TSOP 1 (8×13.4mm)
28-pin DIP, SOJ (300 mil)
®
Note: This part is compatible with both pin numbering
A11
A13
A14
A12
V
WE
OE
A9
A8
A7
A6
A5
A4
A3
CC
conventions used by various manufacturers.
I/O0
I/O1
GND
I/O2
A14
A12
A5
A7
A6
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AS7C256B
Copyright © Alliance Memory. All rights reserved.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
AS7C256B
P. 1 of 8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
CC
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2

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as7c256b Summary of contents

Page 1

... I/ (22) (21) 28 A10 A11 2 CE (23) (20 I/O7 (24) (19 (25) (18) 25 I/O6 A13 5 I/O5 (26) (17 I/O4 (27) (16 (28) (15) 22 I/O3 AS7C256B CC 8 (1) (14) 21 GND A14 9 A12 (2) (13) 20 I/O2 10 (3) (12 I/O1 11 (4) (11 (5) (10 (6) ( (7) ( Note: This part is compatible with both pin numbering conventions used by various manufacturers ...

Page 2

... I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C256B is packaged in high volume industry standard packages. ...

Page 3

... AS7C256B-12 Min – – – = 0mA IH – = 0mA –0.2V CC – (2) = Min – Min 2 Test conditions V = 3dV 3dV out AS7C256B Unit V +0 Max Unit 5 µA 5 µA 160 0.4 V – V Max Unit ...

Page 4

... OH t CLZ t CHZ t OLZ t OHZ Falling input 3,6,7 Data valid 3,6,8 OLZ Data valid 50% Alliance Memory AS7C256B AS7C256B-12 Min Max Unit 12 – ns – – – – – – – ...

Page 5

... Data valid 10, Data valid Alliance Memory AS7C256B Max Unit Notes – – – – – – – – – ...

Page 6

... C=30pF, except on High Z and Low Z parameters, where C=5pF. 12/5/06; V.1.0 ® . See Figure required to meet I specification Alliance Memory Thevenin equivalent Ω 168 D +1.72V (5V) out V CC Ω 480 D out Ω (13) 255 C GND Figure B: Output load ± 200mV from steady-state voltage AS7C256B ...

Page 7

... Min 0.010 B 0.040 b α 0.014 c c 0.008 0.295 E1 0.278 e 0.100 BSC eA 0.330 L 0.120 a 0° AS7C256B Max in mils 0.140 - 0.105 0.730 0.285 0.305 0.347 Max 1.20 0.20 1.05 0.25 0.20 11.80 13.50 0.70 5° Max in mils 0.180 - 0.065 0.022 0.014 1.400 0.320 0.298 0.380 0.140 15° ...

Page 8

... Alliance against all claims arising from such use. ® AS7C256B-12PIN AS7C256B-12JIN AS7C256B-12TIN X I Package: P=DIP 300 mil Temperature range: J=SOJ 300 mil I = -40C to 85C T=TSOP 8x13.4 mm AS7C256B X N=Lead Free Part Copyright © Alliance Memory All Rights Reserved Part Number: AS7C256B Document Version: v.1.0 ...

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