as7c1024c Alliance Memory, Inc, as7c1024c Datasheet - Page 6

• Manufacturer Part Number: as7c1024c
• Description: 5v 128k X 8 Cmos Sram
• Manufacturer: Alliance Memory, Inc

12/5/06, v. 1.0
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
During V
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
t
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CLZ
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
+3.0V
and t
GND
CC
CHZ
power-up, a pull-up resistor to V
10%
are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage.
Figure A: Input pulse
90%
3 ns
90%
10%
CC
on CE is required to meet I
Alliance Memory
Figure B: 5 V Output load
D
OUT
255 Ω
SB
+5 V
480 Ω
C
GND
specification.
13
®
D
OUT
Thevenin equivalent:
168 Ω
+1.728 V
AS7C1024C
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