as7c513c Alliance Memory, Inc, as7c513c Datasheet - Page 6

• Manufacturer Part Number: as7c513c
• Description: 5 V 32k X 16 Cmos Sram
• Manufacturer: Alliance Memory, Inc

Write waveform 2 (CE controlled)
AC test conditions
Notes:
1
2
3
4
5
6
7
8
9
10 N/A.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
Data
Address
12/5/06, v 1.0
LB, UB
During V
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
These parameters are specified with C
This parameter is guaranteed, but not tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Data
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5
OUT
WE
+3.0V
CE
GND
IN
CC
power-up, a pull-up resistor to V
10%
Figure A: Input pulse
90%
3 ns
high Z
t
CLZ
90%
L
t
AS
10%
= 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage.
CC
on CE is required to meet I
11
Data undefined
Alliance Memory
Figure B: 5 V Output load
D
OUT
255 Ω
t
AW
t
t
t
t
WC
CW
BW
WZ
SB
specification.
®
+5 V
480 Ω
C
GND
t
WP
13
t
DW
D
OUT
Data valid
Thevenin Equivalent:
high Z
168 Ω
t
t
AH
WR
t
DH
t
OW
+1.728 V
AS7C513C
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