as6c62256a Alliance Memory, Inc, as6c62256a Datasheet

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as6c62256a

Manufacturer Part Number
as6c62256a
Description
32k?x?8?bit?low?power?cmos?sram
Manufacturer
Alliance Memory, Inc
Datasheet

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F
P
 
APRIL 2009 
APRIL/2009 
EATURES
IN 
32768x8 bit static CMOS RAM
Access times 70 ns
Common data inputs and data
outputs
Three-state outputs
Typ. operating supply current
TTL/CMOS-compatible
Automatical reduction of power
dissipation in long Read Cycles
Power supply voltage 5V + 10%
Operating temperature ranges
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Packages: PDIP28 (600 mil)
C
ONFIGURATION
o
o
o
 
70 ns: 50 mA
0 to 70 °C
-40 to 85 °C
SOP28 (330 mil)
 
32K X 8 BIT LOW POWER CMOS SRAM
D
The AS6C62256A is a static RAM
manufactured using a CMOS
process technology with the
following operating modes:
The memory array is based on a 6-
transistor cell.
The circuit is activated by the falling
edge of E. The address and control
inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the data
outputs are activated by the falling
edge of G, afterwards the data word
read will be available at the outputs
DQ0-DQ7. After the address
change, the data outputs go High-Z
until the new information read is
available. The data outputs have not
preferred state.
ESCRIPTION
- Read
- Write
ALLIANCE MEMORY
 
- Standby
- Data Retention
P
IN 
 
D
ESCRIPTION
 
The Read cycle is finished by the
falling edge of W, or by the rising
edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required.
AS6C62256A 
PAGE 1 of 10

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as6c62256a Summary of contents

Page 1

... IN  ONFIGURATION   APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM D   ESCRIPTION The AS6C62256A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based transistor cell ...

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... APRIL 2009        APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C62256A      PAGE 2 of 10 ...

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... APRIL 2009        APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C62256A      PAGE 3 of 10 ...

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... APRIL 2009        APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C62256A    PAGE 4 of 10 ...

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... APRIL 2009            APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C62256A      PAGE 5 of 10 ...

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... APRIL 2009          APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C62256A    PAGE 6 of 10 ...

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... SOP28 (330 mil) -70 X Package Option: Access P=28pin 600mil PDIP Time S=28pin 330mil SOP ALLIANCE MEMORY AS6C62256A  Operating Temp Commercial – Industrial~ 40 C– Temperature Range Lead Free C = Commercial ( RoHS I = Industrial ( compliant part PAGE  ...

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... APRIL 2009            APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C62256A      PAGE 8 of 10 ...

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... APRIL 2009      APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C62256A      PAGE 9 of 10 ...

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... APRIL/2009    32K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C62256A  Copyright © Alliance Memory   All Rights Reserved PAGE 10 of 10 ...

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