as6c2008 Alliance Memory, Inc, as6c2008 Datasheet - Page 6

• Manufacturer Part Number: as6c2008
• Description: 256k X 8 Bit Low Power Cmos Sram
• Manufacturer: Alliance Memory, Inc

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, t
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
6.t
Rev. 1.1
Address
Address
placed on the bus.
impedance state.
OW
WE#
WE#
Dout
Dout
CE#
CE2
CE#
CE2
Din
Din
February 2007
10/February/07, v.1.0
and t
WHZ
are specified with C
t
AS
t
L
AS
= 5pF. Transition is measured ±500mV from steady state.
t
WHZ
(4)
(4)
t
WHZ
Alliance Memory Inc.
WP
t
AW
t
must be greater than t
t
AW
CW
t
WP
t
WP
t
t
t
WC
WC
CW
256K X 8 BIT LOW POWER CMOS SRAM
®
t
t
DW
DW
High-Z
High-Z
WHZ
Data Valid
Data Valid
+ t
DW
to allow the drivers to turn off and data to be
t
WR
t
t
DH
DH
t
T
WR
OW
(4)
Page 6 of 13
AS6C2008