as6c4008 Alliance Memory, Inc, as6c4008 Datasheet - Page 4
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as6c4008
Manufacturer Part Number
as6c4008
Description
512k X 8 Bit Low Power Cm 512k X 8 Bit Low Power Cmos Sram
Manufacturer
Alliance Memory, Inc
Datasheet
1.AS6C4008.pdf
(15 pages)
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WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, t
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.t
Address
Address
placed on the bus.
OW
WE#
WE#
Dout
Dout
CE#
CE#
Din
Din
OCTOBER 2007
10/OCTOBER/07, V.1.1
and t
WHZ
are specified with C
t
AS
t
512K X 8 BIT LOW POWER CMOS SRAM
L
AS
= 5pF. Transition is measured ±500mV from steady state.
t
(4)
WHZ
(4)
t
WHZ
Alliance Memory Inc.
t
WP
AW
t
t
AW
must be greater than t
CW
t
WP
t
WP
t
t
t
WC
WC
CW
®
t
t
DW
DW
High-Z
High-Z
WHZ
Data Valid
Data Valid
+ t
DW
to allow the drivers to turn off and data to be
t
WR
t
t
DH
DH
t
T
WR
OW
(4)
Page 4 of 15
AS6C4008