bs62lv4005sti Brillance Semiconductor, bs62lv4005sti Datasheet - Page 7

• Manufacturer Part Number: bs62lv4005sti
• Description: Power/voltage Cmos Sram 512k
• Manufacturer: Brillance Semiconductor

R0201-BS62LV4005
WRITE CYCLE2
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
3. T
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
6. OE is continuously low (OE = V
7. D
8. D
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
10. Transition is measured
11. T
ADDRESS
CE
WE
D
D
IN
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
to the outputs must not be applied.
transition, output remain in a high impedance state.
opposite phase to the outputs must not be applied to them.
OUT
WR
The parameter is guaranteed but not 100% tested.
OUT
OUT
BSI
CW
is measured from the earlier of CE or WE going high at the end of write cycle.
is the same phase of write data of this write cycle.
is the read data of next address.
is measured from the later of CE going low to the end of write.
(1,6)
±
500mV from steady state with C
IL
t
).
AS
(5)
t
(4,10)
WHZ
t
AW
7
t
t
t
L
CW
WC
WP
= 5pF as shown in Figure 1B.
(11)
(2)
t
DW
t
DH
BS62LV4005
(8,9)
t
(7)
DH
Revision 2.4
April 2002
(8)