LMH1981MT National Semiconductor Corporation, LMH1981MT Datasheet - Page 10

• Manufacturer Part Number: LMH1981MT
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
HSync’s typical peak-to-peak jitter can be measured using
the input-referred jitter test methodology on a real-time digi-
tal oscilloscope by triggering at or near the input’s O
ence and monitoring HSync’s leading edge with 4-sec. vari-
able persistence. This is one way to measure HSync’s
typical peak-to-peak jitter in the time domain. Figure 11
shows an oscilloscope screenshot demonstrating very low
jitter on HSync’s leading edge for a 1080I video input.
Vertical Sync Output
VSOUT (pin 8) produces a negative-polarity vertical sync
signal, or VSync. VSync’s negative-going leading edge is
derived from O
propagation delay, and its output pulse width, T
approximately three horizontal periods (3H).
Burst/Back Porch Timing Output
BPOUT (pin 13) provides a negative-polarity burst/back
porch signal, which is pulsed low for a fixed width during the
back porch interval following the input’s sync pulse. The
burst/back porch timing pulse is useful as a burst gate signal
for NTSC/PAL color burst synchronization and as a clamp
Upper: Horizontal Sync Leading Edge (Reference)
FIGURE 11. Typical HSync Jitter for 1080I Input
Lower: Zoomed In — 400 ps/DIV, 25 mV/DIV
H
of the first vertical serration pulse with a
(Continued)
VSOUT
20174513
H
, spans
refer-
10
signal for black level clamping (DC restoration) and sync
stripping applications.
For SDTV formats, the back porch pulse’s negative-going
leading edge is derived from the input’s positive-going sync
edge with a propagation delay, and the pulse width spans an
appropriate duration of the color burst envelope for NTSC/
PAL. During the vertical interval, its pulse width is shorter to
correspond with the narrow serration pulses. For EDTV for-
mats, the back porch pulse behaves similar to the SDTV
case except that the shorter pulse width is always main-
tained. For HDTV formats, the pulse’s leading edge is de-
rived from the input’s negative-going trailing sync edge with
a propagation delay, and the pulse width is even narrower to
correspond with the shortest back porch duration of HDTV
formats.
Odd/Even Field Output
OEOUT (pin 14) provides an odd/even field output signal,
which facilitates identification of odd and even fields for
interlaced or segmented frame (sF) formats. For interlaced
or segmented frame formats, the odd/even output is logic
high during an odd field (field 1) and logic low during an even
field (field 2). The odd/even output edge transitions align with
VSync’s leading edge to designate the start of odd and even
fields. For progressive (non-interlaced) video formats, the
output is held constantly at logic high.
Video Format Output (Lines-per-Field Data)
The LMH1981 counts the number of HSync pulses per field
to approximate the total horizontal line count per field (verti-
cal resolution). This can be used to identify the video format
and enable dynamic adjustment of video system param-
eters, such as color space or scaler conversions. The line
count per field is output to VFOUT (pin 9) as an 11-bit binary
data stream. The video format data stream is clocked out on
the 11 consecutive leading edges of HSync, starting at the
3rd HSync after each VSync leading edge. Outside of these
active 11-bits of data, the video format output can be either 0
or 1 and should be treated as undefined. Refer to Figure 12
and Figure 13 to see the VFOUT data timing for the 1080I
interlaced format and Figure 14 for the 480P progressive
format.
A FPGA/MCU can be used to decode the 11-bit VFOUT data
stream by using HSync as the clock source signal and
VSync as the enable signal. Using the FPGA’s clock delay
capability, a delayed clock derived from HSync can be used
as the sampling clock to latch the VFOUT data in the middle
of the horizontal line period rather than near the VFOUT
data-bit transitions in order to avoid setup time requirements.