LMH1981MT National Semiconductor Corporation, LMH1981MT Datasheet - Page 9

• Manufacturer Part Number: LMH1981MT
• Manufacturer: National Semiconductor Corporation

Application Information
delay, or reduced input sync amplitude range) against tem-
perature, supply voltage, input signal, or part-to-part varia-
tions.
Note: The R
“R
older LM1881, the R
date different input line rates. For the LMH1981, the R
value is fixed, and the device automatically detects the input
line rate to support various video formats without electrical or
physical intervention.
Automatic Format Detection and Switching
Automatic format detection eliminates the need for external
programming via a microcontroller or R
device outputs will respond correctly to video format switch-
ing after a sync lock period has been satisfied. Unlike other
sync separators, the LMH1981 does not require the power to
be cycled in order to guarantee correct outputs after a sig-
nificant change to the input signal. See the Sync Lock
Period sub-section for more details.
50% Sync Slicing
The LMH1981 features 50% sync slicing to provide accurate
sync separation for a video input amplitudes from 0.5 V
2 V
even for improperly terminated or attenuated source signals
and stability against variations in temperature. The sync
separator is compatible with SD/EDTV bi-level and HDTV
tri-level sync inputs. Bi-level syncs will be sliced at the 50%
point between the video blanking level and negative sync tip,
indicated by the input’s sync timing reference or “O
Figure 9. Tri-level syncs will be sliced at the 50% point
between the negative and positive sync tips (or positive
zero-crossing), indicated by O
Macrovision Compatibility
The LMH1981 is compatible with the Macrovision Video
Copy Protection System commonly used in VHS and DVD
video sources, which inserts pseudo-sync pulses in the
video signal during the vertical blanking interval. These
Macrovision-embedded pulses will be effectively ignored by
the sync separator, and the outputs will not be affected.
VIDEO INPUT
Supported Video Standards
The LMH1981 supports sync separation for the following
video interfaces and standards:
The LMH1981 does not support RGB formats that conform
to VESA standards used for PC graphics.
Video Input Requirements
V
and G (Sync on Green) from GBR with bi-level sync or
• Composite Video (CVBS) and S-Video (Y/C):
• Component Video (YP
IN
SET
— SDTV: SMPTE 170M (NTSC), ITU-R BT.470 (PAL),
— SDTV: SMPTE 125M, SMPTE 267M, ITU-R BT.601
— EDTV: ITU-R BT.1358 (480P, 576P)
— HDTV: SMPTE 296M (720P), SMPTE 274M (1080I/
PP
(pin 4) accepts CVBS, Y (Luma) from Y/C and YP
SECAM
(480I, 576I)
P), SMPTE RP 211 (1080PsF)
, which enables excellent HSync jitter performance
resistor” used in the LM1881 sync separator. In the
EXT
resistor serves a different function than the
SET
value was adjusted to accommo-
B
P
R
/GBR):
H
in Figure 10.
SET
(Continued)
resistor. The
PP
H
B
” in
EXT
P
R
to
,
9
tri-level sync. The video source should be terminated with a
75Ω load resistor to ensure correct input signal amplitude
and minimize video & sync distortion due to reflections. In
extreme cases, the LMH1981 can handle unterminated and
double-terminated input conditions assuming a typical 1 V
video signal.
The video input signal should be AC coupled through a
properly chosen capacitor value in order to optimize the
trade-off between the sync lock period and the line droop
voltage at V
AC coupling capacitor will reduce the jitter on HSync but
increase the sync lock period, since higher value capacitors
take more time to reach a quiescent DC voltage via the
clamp charging current. A 1 µF coupling capacitor is a good
starting value for typical applications and can be adjusted to
meet the specific application requirements.
Sync Lock Period
When there is a significant change to the video input condi-
tion, such as applying a new signal, switching the video
format, or looping-through (which may cause double input
termination), the steady-state operation of the LMH1981 will
be affected while its outputs begin to produce new timing
signals. These signals may not be accurate until after an
appropriate start-up time or “sync lock period” has been
satisfied. This is because the AC coupling capacitor needs
time to reestablish its quiescent DC voltage while the internal
50% sync slicing circuitry regains steady-state operation
before the outputs are accurate. T
period from when the new input signal starts and stabilizes at
V
use. It is recommended that the outputs are used only after
T
LOGIC OUTPUTS
In the absence of a video input signal, the LMH1981 outputs
are logic high except for the odd/even field and video format
outputs, which are both undefined, and the composite sync
output.
Composite Sync Output
CSOUT (pin 12) simply reproduces the video input sync
pulses below the video blanking level. This is obtained by
clamping the video signal sync tip to the internal clamp
voltage at V
resultant composite sync signal, or CSync. For both bi-level
and tri-level syncs, CSync’s negative-going leading edge is
derived from the input’s negative-going leading edge with a
propagation delay.
Horizontal Sync Output
HSOUT (pin 7) produces a negative-polarity horizontal sync
signal, or HSync, with very low jitter on its negative-going
leading edge (reference edge). For bi-level and tri-level sync
signals, the horizontal sync leading edge is triggered from
the input’s sync reference, O
HSync was optimized for excellent jitter performance on its
leading edge because most video systems are negative-
edge triggered. When HSync is used in a positive-edge
triggered system, like an FPGA PLL input, it must be inverted
beforehand to produce positive-going leading edges. The
trailing edge of HSync should never be used as the refer-
ence or triggered edge. This is because some trailing edges
of HSync are reconstructed for the broad serration pulses
during the vertical interval.
SYNC-LOCK
IN
to when the output sync signals are accurate and valid to
IN
condition has been satisfied.
IN
, which can affect jitter performance. A larger
and using 50% sync slicing to extract the
H
, with a propagation delay.
SYNC-LOCK
is the maximum
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PP