LMK03001D National Semiconductor Corporation, LMK03001D Datasheet - Page 18

• Manufacturer Part Number: LMK03001D
• Manufacturer: National Semiconductor Corporation

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2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output. In
order for these delays to be active, the respective
CLKoutX_MUX bit must be set to either "Delayed" or "Divided
and Delayed" mode. By adding the delay block to the output
path a fixed delay of approximately 400 ps is incurred in ad-
dition to the delay shown in the table below.
2.3.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is en-
abled or not. If the EN_CLKout_Global bit is set to zero or if
GOE pin is held low, all CLKoutX_EN bit states will be ignored
and all clock outputs will be disabled.
2.4 REGISTER R9
The programming of register R9 is optional. If it is not pro-
grammed the the bit Vboost will be defaulted to 0, which is the
test condition for all electrical characteristics.
2.4.1 Vboost -- Voltage Boost
By enabling this bit, the voltage output levels for all clock out-
puts is increased. Also, the noise floor is improved
2.5 REGISTER R11
This register only has one bit and only needs to be pro-
grammed in the case that the phase detector frequency is
greater than 20 MHz and digital lock detect is used. Other-
wise, it is automatically defaulted to the correct values.
CLKoutX_EN
CLKoutX_DLY[3:0]
Vboost
bit
0
1
0
1
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
EN_CLKout_Global bit = 1
GOE pin = High / No
Voltage Output
Typical LVDS
Conditions
Connect
(mV)
350
390
Delay (ps)
0 (default)
Typical LVPECL
Voltage Output
1050
1200
1350
1500
1650
1800
1950
2100
2250
150
300
450
600
750
900
CLKoutX
Disabled
(mV)
(default)
Enabled
810
865
State
18
2.5.1 DIV4 -- High Phase Detector Frequencies and Lock
Detect
This bit divides the frequency presented to the digital lock de-
tect circuitry by 4. It is necessary to get a reliable output from
the digital lock detect output in the case of a phase detector
frequency frequency greater than 20 MHz.
2.6 REGISTER R13
2.6.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter
Capacitors C3 and C4
These bits control the capacitor values for C3 and C4 in the
internal loop filter.
2.6.2 VCO_R3_LF[2:0] -- Value for Internal Loop Filter
Resistor R3
These bits control the R3 resistor value in the internal loop
filter. The recommended setting for VCO_R3_LF[2:0] = 0 for
optimum phase noise and jitter.
2.6.3 VCO_R4_LF[2:0] -- Value for Internal Loop Filter
Resistor R4
These bits control the R4 resistor value in the internal loop
filter. The recommended setting for VCO_R4_LF[2:0] = 0 for
optimum phase noise and jitter.
VCO_C3_C4_LF[3:0]
DIV4
VCO_R3_LF[2:0]
0
1
12 to 15
5 to 7
10
11
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
Phase Detector Frequency
Phase Detector Frequency > 20 MHz
Digital Lock Detect Circuitry Mode
0 (default)
Divided by 4
Not divided
C3 (pF)
Loop Filter Capacitors
Low (~600 Ω) (default)
100
100
100
150
150
50
50
50
0
0
0
R3 Value (kΩ)
Invalid
Invalid
≤
10
20
30
40
20 MHz (default)
10 (default)
C4 (pF)
110
110
110
160
160
110
60
10
10
60
60