LMK03001D National Semiconductor Corporation, LMK03001D Datasheet - Page 19

• Manufacturer Part Number: LMK03001D
• Manufacturer: National Semiconductor Corporation

2.6.4 OSCin_FREQ[7:0] -- Oscillator Input Calibration
Adjustment
These bits are to be programmed to the OSCin frequency. If
the OSCin frequency is not an integral multiple of 1 MHz, then
round to the closest value.
2.7 REGISTER R14
2.7.1 PLL_R[11:0] -- R Divider Value
These bits program the PLL R Divider and are programmed
in binary fashion. Any changes to PLL_R require R15 to be
programmed again to active the frequency calibration routine.
2.7.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin
These bits set the output mode of the LD pin. The table below
lists several different modes.
0
0
0
0
1
.
.
PLL_MUX[3:0]
OSCin_FREQ[7:0]
VCO_R4_LF[2:0]
0
0
0
0
1
.
.
201 to 255
0
1
2
3
4
5
6
7
8
0
0
0
0
1
.
.
5 to 7
200
10
...
...
0
1
2
3
4
1
2
0
0
0
0
1
.
.
PLL_R[11:0]
0
0
0
0
1
.
.
0
0
0
0
1
.
.
Output Type
Open Drain
Open Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
0
0
0
0
1
.
.
NMOS
PMOS
Hi-Z
0
0
0
0
1
.
.
0
0
0
1
1
Low (~200 Ω) (default)
.
.
OSCin Frequency
10 MHz (default)
0
0
0
0
1
.
.
R4 Value (kΩ)
Invalid
200 MHz
0
0
1
1
1
Analog Lock Detect
Analog Lock Detect
Analog Lock Detect
.
.
Digital Lock Detect
Digital Lock Detect
Invalid
1 MHz
2 MHz
Invalid
Disabled (default)
LD Pin Function
10
20
30
40
...
...
(Active High)
0
1
0
0
1
(Active Low)
.
.
Logic High
Logic Low
PLL R Divide
10 (default)
Invalid
Value
4095
...
...
1
2
19
2.7.3 POWERDOWN bit -- Device Power Down
This bit can power down the device. Enabling this bit powers
down the entire device and all blocks, regardless of the state
of any of the other bits or pins.
2.7.4 EN_CLKout_Global bit -- Global Clock Output
Enable
This bit overrides the individual CLKoutX_EN bits. When this
bit is set to 0, all clock outputs are disabled, regardless of the
state of any of the other bits or pins.
2.7.5 EN_Fout bit -- Fout port enable
This bit enables the Fout pin.
2.8 REGISTER R15
Programming R15 also activates the frequency calibration
routine.
2.8.1 PLL_N[17:0] -- PLL N Divider
These bits program the divide value for the PLL N Divider.
The PLL N Divider follows the VCO Divider and precedes the
PLL phase detector. Since the VCO Divider is also in the
feedback path from the VCO to the PLL Phase Detector, the
total N divide value, N
vider value. N
frequency is calculated as, f
VCO Divider / PLL R Divider. Since the PLL N divider is a pure
binary counter there are no illegal divide values for PLL_N
[17:0] except for 0.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EN_CLKout_Global bit
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
PLL_MUX[3:0]
POWERDOWN bit
12 to 15
EN_Fout bit
10
11
9
0
1
0
1
0
1
Total
PLL_N[17:0]
= PLL N Divider × VCO Divider. The VCO
Output Type
Total
Push-Pull
Push-Pull
, is also influenced by the VCO Di-
Entire Device Powered Down
VCO
Normal Operation (default)
Normal Operation (default)
= f
Disabled (default)
Fout Pin Status
Clock Outputs
OSCin
Invalid
Invalid
Enabled
N Divider Output/2
R Divider Output/2
(50% Duty Cycle)
(50% Duty Cycle)
Mode
All Off
LD Pin Function
× PLL N Divider ×
www.national.com
(default)
Divider
262143
PLL N
Invalid
Value
760
...
...
1