hsp50215 Intersil Corporation, hsp50215 Datasheet - Page 13

• Manufacturer Part Number: hsp50215
• Description: Digital Upconverter
• Manufacturer: Intersil Corporation

The convolution multiplies C0 by the most recent data
sample. For a 16 tap, interpolate-by-4 filter, the calculations
are:
OUTPUT0 = (C0*D[n]) + (C4*D[n-1]) + (C8*D[n-2]) +
(C12*D[n-3])
OUTPUT1 = (C1*D[n]) + (C5*D[n-1]) + (C9*D[n-2]) +
(C13*D[n-3])
OUTPUT2 = (C2*D[n]) + (C6*D[n-1]) + (C10*D[n-2]) +
(C14*D[n-3])
OUTPUT3 = (C3*D[n]) + (C7*D[n-1]) + (C11*D[n-2]) +
(C15*D[n-3])
Table 6 indicates how the I coefficients should be loaded for
this example. Notice that 16 filter coefficients are required.
All other addresses not used. The filter interpolates by 4
and the coefficients are loaded sequentially through the 4
interpolation phases starting at 512 - 515, then jumping to
528 - 531 for the next four addresses, and so on until 16
coefficients have been loaded.
Shaping filter Q coefficients are loaded from the first
coefficient (B0) in address 0x300h to the last address in
0x3FFh. The convolution multiplies B0 by the most recent
data sample. For a 16 tap, interpolate-by-4 filter, the
calculations are:
IP10
IP11
IP12
IP13
IP14
IP15
IP0
IP1
IP2
IP3
IP4
IP5
IP6
IP7
IP8
IP9
DS
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
0
DS
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
1
3-434
DS
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
2
DS
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
3
TABLE 6. Q SHAPING FILTER COEFFICIENT ADDRESSES
DS
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
4
DS
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
5
DS
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
HSP50215
6
DS
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
7
OUTPUT0 = (B0*D[n]) + (B4*D[n-1]) + (B8*D[n-2]) +
(B12*D[n-3])
OUTPUT1 = (B1*D[n]) + (B5*D[n-1]) + (B9*D[n-2]) +
(B13*D[n-3])
OUTPUT2 = (B2*D[n]) + (B6*D[n-1]) + (B10*D[n-2]) +
(B14*D[n-3])
OUTPUT3 = (B3*D[n]) + (B7*D[n-1]) + (B11*D[n-2]) +
(B15*D[n-3])
Table 7 indicates how the Q coefficients should be loaded for
this example. Identical to the I filter, notice that since 16 filter
coefficients are required. All other addresses not used. The
filter interpolates by 4, and the coefficients are loaded
sequentially through the 4 interpolation phases, starting at
768-771, then jumping to 784-787 for the next four addresses,
and so on until 16 coefficients have been loaded.
Microprocessor Read
The DUC offers the microprocessor access to all of the
control data configuration registers through a read process.
The shaping filter coefficients, however, cannot be read.
With CE asserted, a “read” consists of dropping the RD line
low to transfer data from the register addresses selected by
A(9:0). The read address mapping is provided in Table 8.
The timing is detailed in Figure 15.
DS
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
8
DS
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
9
DS
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
10
DS
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
11
DS
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
12
DS
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
13
DS
1000
1001
1002
1003
1004
1005
1006
1007
992
993
994
995
996
997
998
999
14
DS
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
15