hsp50215 Intersil Corporation, hsp50215 Datasheet - Page 15

• Manufacturer Part Number: hsp50215
• Description: Digital Upconverter
• Manufacturer: Intersil Corporation

Reset
There are two ways to invoke a reset in the DUC: Assert the
RST signal, or write to Control Word 21. While a reset does
not stop the internal clocking, the data processing halts
because of the following actions:
• Zeros are placed into the Sample Rate and Carrier NCO
• The I and Q FIFO depth counters are reset to zero and the
• The data path is disabled between the shaping filter and
• In the interpolation filter, the coefficient RAM select is
Commanding the DUC to reset by asserting the RST signal
causes the all internal processing to halt. Furthermore,
asserting RST clears both the Sampling and Carrier NCO
frequency accumulator registers (sets the outputs = 0). The
center and offset frequency registers are not cleared by
RST. The NCO accumulator registers are held at zero until
the NCO is loaded with the first frequency value. The
Sampling and Carrier NCO center and offset frequency
registers are held at zero until an input sync has been
detected. Because the Sampling NCO does not start until
the detection of a sync (after a RST assertion), the shaping
FIR filter is also kept from processing data. Reset is
performed by either dropping the RST low or writing to
Control Word 21 (see Microprocessor Write).
accumulator registers. These registers will be held at zero
until a sync enables the NCOs to again accept the
frequency input word.
FIFORDY flipflop is Cleared, pulling the DUC FIFORDY
output high.
the FM modulator in the prefiltered FM mode, and the
Gain adjust circuit in the QASK mode.
disabled, the data into the data RAM is set to zeroes, the
Q channel data RAM select is disabled and the Data RAM
address is zeroed, beginning a 16 address increment to
both the I and Q Data RAMS. This enables the data
RAMS to be written with zeros.
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HSP50215
Starting Sequence
DUC internal processing can be initiated by either pulsing
the SYNCIN pin (when it must be synchronized to a system
event) or by writing to the LSByte of the Sampling NCO
center frequency Control Word. The start up for the SYNCIN
pin occurs on either the rising or falling edge of the pulse,
whichever is selected in CW22, Bit 1.
For multiple DUC operation, the SYNCOUT of the first chip
acts as a master and is tied to the SYNCIN of the remaining
chips, as shown in Figure 16. When the first chip receives an
input sync from a write to the LSByte of the timing NCO
control word, then the SYNCOUT will synchronize all other
DUC’s slaved to that chip.
FIGURE 16. CONFIGURATION FOR SYNCHRONIZATION OF
MULTIPLE DUCs
HSP50215
HSP50215
HSP50215
SYNCOUT
SYNCIN
SYNCIN
SYNCIN