adf7023-j Analog Devices, Inc., adf7023-j Datasheet - Page 35

• Manufacturer Part Number: adf7023-j
• Description: High Performance, Low Power, Ism Band Fsk/gfsk/msk/gmsk Transceiver Ic
• Manufacturer: Analog Devices, Inc.

SPORT MODE
It is possible to bypass all of the packet management features of
the ADF7023-J and use the sport interface for transmit and receive
data. The sport interface is a high speed synchronous serial
interface allowing direct interfacing to processors and DSPs.
Sport mode is enabled using the DATA_MODE setting in the
PACKET_LENGTH_CONTROL register (Address 0x126), as
described in Table 13. The sport mode interface is on the GPIO
pins (GP0, GP1, GP2, GP4, and XOSC32KP_GP5_ATB1). These
GPIO pins can be configured using the GPIO_CONFIGURE
setting (Address 0x3FA), as described in Table 14.
Sport mode provides a receive interrupt source on GP4. This
interrupt source can be configured to provide an interrupt, or
strobe signal, on either preamble detection or sync word detection.
The type of interrupt is configured using the GPIO_CONFIGURE
setting.
PACKET STRUCTURE IN SPORT MODE
In sport mode, the host processor has full control over the packet
structure. However, the preamble frame is still required to allow
sufficient bits for receiver settling (AGC, AFC, and CDR). In
sport mode, sync word detection is not mandatory in the ADF7023-J
but can be enabled to provide byte level synchronization for the host
processor via the sync word detect interrupt or strobe on GP4. The
general format of a sport mode packet is shown in Figure 48.
SPORT MODE IN TRANSMIT
Figure 49 illustrates the operation of the sport interface in
transmit. Once in the PHY_TX state with sport mode enabled,
the data input of the transmitter is fully controlled by the sport
interface (Pin GP1). The transmit clock appears on the GP2 pin.
The transmit data from the host processor should be synchronized
with this clock. The FW_STATE variable in the status word (see
Table 13. SPORT Mode Setup
DATA_MODE Bits in
PACKET_LENGTH_
CONTROL Register
DATA_MODE = 0
DATA_MODE = 1
DATA_MODE = 2
PREAMBLE
Figure 48. General Sport Mode Packet
WORD
SYNC
Description
Packet mode enabled. Packet management is
controlled by the communications processor.
Sport mode enabled. The Rx data and Rx clock are
enabled in the PHY_RX state (GPIO_CONFIGURE =
0xA0, 0xA3, 0xA6). The Rx clock is enabled in the
PHY_RX state, and Rx data is enabled on the preamble
detect (GPIO_CONFIGURE = 0xA1, 0xA2, 0xA4, 0xA5,
0xA7, 0xA8).
Sport mode enabled. The Rx data and Rx clock are
enabled in the PHY_RX state if GPIO_CONFIGURE =
0xA0, 0xA3, 0xA6. The Rx clock is enabled in the
PHY_RX state, and Rx data is enabled on the preamble
detect if GPIO_CONFIGURE = 0xA1, 0xA2, 0xA4, 0xA5,
0xA7, 0xA8.
PAYLOAD
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the Status Word section) or the CMD_FINISHED interrupt (see
the Interrupts in Sport Mode section) can be used to indicate
when the ADF7023-J has reached the PHY_TX state and,
therefore, is ready to begin transmitting data. The ADF7023-J
keeps transmitting the serial data presented at the GP1 input
until the host processor issues a command to exit the PHY_TX state.
SPORT MODE IN RECEIVE
The sport interface supports the receive operation with a number
of modes to suit particular signaling requirements. The receive
data appears on the GP0 pin, whereas the receive synchronized
clock appears on the GP2 pin. The GP4 pin provides a dedicated
SPORT mode interrupt or strobe signal on either preamble or
sync word detection, as described in Table 13 and Table 14.
Once enabled, the interrupt signal and strobe signals remain
operational while in the PHY_RX state. The strobe signal gives
a single high pulse of 1-bit duration every eight bits. The strobe
signal is most useful when used with sync word detection because
it is synchronized to the sync word and strobes the first bit in
every byte.
In SPORT mode, IRQ_GP3 retains its normal interrupt
functionality for INTERRUPT_SOURCE_1; however, only
INTERRUPT_PREAMBLE_DETECT and INTERRUPT_
SYNC_DETECT are available from INTERRUPT_SOURCE_0.
Refer to the Interrupt Generation section for more details.
TRANSMIT BIT LATENCIES IN SPORT MODE
The transmit bit latency is the time from the sampling of a bit
by the transmit data clock on GP2 to when that bit appears at
the RF output. There is no transmit bit latency when using
2FSK/MSK modulation. The latency when using GFSK/GMSK
modulation is two bits. It is important that the host processor
keep the ADF7023-J in the PHY_TX state for two bit periods
after the last data bit is sampled by the data clock to account for
this latency when using GMSK/GFSK modulation.
GPIO Configuration
GP0: Rx data
GP1: Tx data
GP2: Tx/Rx clock
GP4: interrupt or strobe enabled on preamble detect
(depends on GPIO_CONFIGURE)
XOSC32KP_GP5_ATB1: depends on GPIO_CONFIGURE
GP0: Rx data
GP1: Tx data
GP2: Tx/Rx clock
GP4: interrupt or strobe enabled on sync word detect
(depends on GPIO_CONFIGURE)
XOSC32KP_GP5_ATB1: depends on GPIO_CONFIGURE
ADF7023-J