adf7023-j Analog Devices, Inc., adf7023-j Datasheet - Page 80

• Manufacturer Part Number: adf7023-j
• Description: High Performance, Low Power, Ism Band Fsk/gfsk/msk/gmsk Transceiver Ic
• Manufacturer: Analog Devices, Inc.

ADF7023-J
Table 49. Packet RAM Memory
Address
0x000
0x001
0x002
0x003
0x004
0x005 to 0x00B
0x00D
0x00E to 0x00F
0x010 to 0x018
1
BBRAM REGISTER DESCRIPTION
Table 50. 0x100: INTERRUPT_MASK_0
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Table 51. 0x101: INTERRUPT_MASK_1
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Only valid on power-up or wake-up from the PHY_SLEEP state because the communications processor overwrites these values on exit from the PHY_ON state.
1
1
1
1
Name
INTERRUPT_NUM_WAKEUPS
INTERRUPT_SWM_RSSI_DET
INTERRUPT_AES_DONE
INTERRUPT_TX_EOF
INTERRUPT_ADDRESS_MATCH
INTERRUPT_CRC_CORRECT
INTERRUPT_SYNC_DETECT
INTERRUPT_PREMABLE_DETECT
Name
BATTERY_ALARM
CMD_READY
Reserved
WUC_TIMEOUT
Reserved
Reserved
SPI_READY
CMD_FINISHED
Register
VAR_COMMAND
Product code, most significant byte = 0x70
Product code, least significant byte = 0x23
Silicon revision code, most significant byte
Silicon revision code, least significant byte
Reserved
VAR_TX_MODE
Reserved
Custom PLL loop filter look-up table
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Interrupt when the number of WUC wake-ups (NUMBER_OF_WAKEUPS[15:0]) has
reached the threshold (NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0])
1: interrupt enabled; 0: interrupt disabled
Interrupt when the measured RSSI during smart wake mode has exceeded the
RSSI threshold value (SWM_RSSI_THRESH, Address 0x108)
1: interrupt enabled; 0: interrupt disabled
Interrupt when an AES encryption or decryption command is complete; available
only when the AES firmware module has been loaded to the ADF7023-J program RAM
1: interrupt enabled; 0: interrupt disabled
Interrupt when a packet has finished transmitting
1: interrupt enabled; 0: interrupt disabled
Interrupt when a received packet has a valid address match
1: interrupt enabled; 0: interrupt disabled
Interrupt when a received packet has the correct CRC
1: interrupt enabled; 0: interrupt disabled
Interrupt when a qualified sync word has been detected in the received packet
1: interrupt enabled; 0: interrupt disabled
Interrupt when a qualified preamble has been detected in the received packet
1: interrupt enabled; 0: interrupt disabled
Interrupt when the WUC has timed out
Description
Interrupt when the battery voltage has dropped below the threshold value
(BATTERY_MONITOR_THRESHOLD_VOLTAGE, Address 0x32D)
1: interrupt enabled; 0: interrupt disabled
Interrupt when the communications processor is ready to load a new command;
mirrors the CMD_READY bit of the status word
1: interrupt enabled; 0: interrupt disabled
1: interrupt enabled; 0: interrupt disabled
Interrupt when the SPI is ready for access
1: interrupt enabled; 0: interrupt disabled
Interrupt when the communications processor has finished performing a
command
1: interrupt enabled; 0: interrupt disabled
Rev. 0 | Page 80 of 100
R/W
R/W
R
R
R
R
R
R/W
R
R/W