cyrf6936 Cypress Semiconductor Corporation., cyrf6936 Datasheet - Page 19

• Manufacturer Part Number: cyrf6936
• Description: Wirelessusb Lp 2.4 Ghz Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-16015 Rev. *G
Mnemonic
Bit
Default
Read/Write
Function
Bit 7
Bit 6
Bit 5
Bits 3:2
Bits 1:0
The order of writing these bits impacts the value of the Sleep current I
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:6
Bit 5
Bits 2:0
Power Management Unit (PMU) Enable. Setting this bit enables the PMU only if PMU Mode Force (bit 5) is set. Otherwise it
has no effect. See PMU Mode Force (bit 5) description for more information.
Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the V
falls below the threshold set by LVI TH, a low voltage interrupt is generated. The LVI is not available when the device is in sleep
mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled.
PMU Mode Force. If this bit is set, the PMU operation is based on the state of the PMU Enable Bit (bit 7). if this bit is not set
then the PMU is disabled in Sleep mode and enabled when not in Sleep mode, if Bit 7 = 1. If Bit 7 = 1 and Bit 5 = 1, PMU is
enabled always (even during sleep). If Bit 7 = 0 and Bit 5 = 1, PMU is disabled always. If Bit 7 = 1and Bit 5 = 0, PMU is disabled
only in Sleep Mode.
Low Voltage Interrupt Threshold. This field sets the voltage on V
01 = 2.2V; 00 = PMU OUTV voltage.
PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V; 10 = 2.5V; 01 = 2.6V; 00 = 2.7V. When
the PMU is active, the voltage output by the PMU on V
V
XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT
FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire
mode then the MISO pin outputs a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to GPIO
mode, and set the GPIO state in IO_CFG_ADR.
Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event
when the crystal has stabilized after the device has awaken from sleep mode. This event is cleared by writing ‘0’ to this bit.
XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz; 1 = 6 MHz,
2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
REG
PMU EN
pin is less than the specified maximum value, and the voltage in V
R/W
R/W
7
0
7
1
XOUT FN
LVIRQ EN
R/W
R/W
6
0
6
0
XTAL_CTRL_ADR
PWR_CTRL_ADR
PMU Mode
XSIRQ EN
Force
R/W
R/W
5
1
5
0
PFET Disable
Not Used
REG
SB
4
4
-
-
-
-
.
is never less than this voltage, provided that the total load on the
BAT
at which the LVI is triggered. 11 = 1.8V; 10 = 2.0V;
Not Used
R/W
3
0
BAT
3
-
-
is greater than the specified minimum value.
LVI TH
R/W
R/W
2
1
2
0
FREQ
R/W
R/W
Address
Address
1
0
1
0
PMU OUTV
CYRF6936
Page 19 of 40
BAT
voltage
R/W
R/W
0
0
0
0
0x0B
0x0C
[+] Feedback