cyrf6936 Cypress Semiconductor Corporation., cyrf6936 Datasheet - Page 20

• Manufacturer Part Number: cyrf6936
• Description: Wirelessusb Lp 2.4 Ghz Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-16015 Rev. *G
Mnemonic
Bit
Default
Read/Write
Function
To use a GPIO pin as an input, the output mode must be set to open drain, and ‘1’ written to the corresponding output register bit.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
Bit
Default
Read/Write
Function
To use a GPIO pin as an input, the output mode must be set to open drain, and a ‘1’ written to the corresponding output register bit.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRQ Pin Drive Strength. Setting this bit configures the IRQ pin as an open drain output. Clearing this bit configures the IRQ pin
as a standard CMOS output, with the output ‘1’ drive voltage being equal to the V
IRQ Polarity. Setting this bit configures the IRQ signal polarity to be active HIGH. Clearing this bit configures the IRQ signal
polarity to be active low.
MISO Pin Drive Strength. Setting this bit configures the MISO pin as an open drain output. Clearing this bit configures the
MISO pin as a standard CMOS output, with the output ‘1’ drive voltage being equal to the V
XOUT Pin Drive Strength. Setting this bit configures the XOUT pin as an open drain output. Clearing this bit configures the
XOUT pin as a standard CMOS output, with the output ‘1’ drive voltage being equal to the V
PACTL Pin Drive Strength. Setting this bit configures the PACTL pin as an open drain output. Clearing this bit configures the
PACTL pin as a standard CMOS output, with the output ‘1’ drive voltage being equal to the V
PACTL Pin Function. When this bit is set, the PACTL pin is available for use as a GPIO.
SPI Mode. When this bit is cleared, the SPI interface acts as a standard 4-wire SPI Slave interface. When this bit is set, the SPI
interface operates in “3-Wire Mode” combining MISO and MOSI on the same pin (SDAT). The MISO pin is available as a GPIO
pin.
IRQ Pin Function. When this bit is cleared, the IRQ pin is asserted when an IRQ is active; the polarity of this IRQ signal is con-
figurable in IRQ POL. When this bit is set, the IRQ pin is available for use as a GPIO pin, and the IRQ function is multiplexed
onto the MOSI pin. In this case the IRQ signal state is presented on the MOSI pin whenever the SS signal is inactive (HIGH).
XOUT Output. When the XOUT pin is configured to be a GPIO, the state of this bit sets the output state of the XOUT pin.
MISO Output. When the MISO pin is configured to be a GPIO, the state of this bit sets the output state of the MISO pin.
PACTL Output. When the PACTL pin is configured to be a GPIO, the state of this bit sets the output state of the PACTL pin.
IRQ Output. When the IRQ pin is configured to be a GPIO, the state of this bit sets the output state of the IRQ pin.
XOUT Input. The state of this bit reflects the voltage on the XOUT pin.
MISO Input. The state of this bit reflects the voltage on the MISO pin.
PACTL Input. The state of this bit reflects the voltage on the PACTL pin.
IRQ Input. The state of this bit reflects the voltage on the IRQ pin.
XOUT OP
IRQ OD
R/W
R/W
7
0
7
0
MISO OP
IRQ POL
R/W
R/W
6
0
6
0
GPIO_CTRL_ADR
IO_CFG_ADR
PACTL OP
MISO OD
R/W
R/W
5
0
5
0
XOUT OD
IRQ OP
R/W
R/W
4
0
4
0
PACTL OD
XOUT IP
R/W
R
3
0
3
-
IO
PACTL GPIO
pin voltage.
MISO IP
R/W
R
2
0
2
-
IO
IO
IO
pin voltage.
pin voltage.
pin voltage.
PACTL IP
SPI 3PIN
Address
R/W
Address
R
1
0
1
-
CYRF6936
Page 20 of 40
IRQ GPIO
IRQ IP
R/W
R
0
0
0
-
0x0D
0x0E
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