ep1m120 Altera Corporation, ep1m120 Datasheet - Page 51

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Figure 28. IOE Configured for DDR Output
Local Interconnect
Associated LAB
Local Fast
Two Row
Signals
Six Fast
Signals
Global
Dedicated
Clocks
Four
When using the IOE for double data rate outputs, the output register and
OE register are automatically configured to clock two data paths from LEs
on rising clock edges. These register outputs are multiplexed by the clock
to drive the output pin at a 2 rate. The output register clocks the first bit
out on the clock high time, while the OE register clocks the second bit out
on the clock low time.
output.
Bidirectional DDR on an I/O pin is possible by using the IOE for DDR
output and using LEs to acquire the double data rate input. Bidirectional
DDR I/O pins support double data rate synchronous DRAM (DDR
SDRAM) at 166 MHz (334 Mbps), which transfer data on a double data
rate bidirectional bus. QDR SRAMs are also supported with DDR I/O
pins on separate read and write ports.
Chip-Wide Reset
Output Register
OE Register
D
CLRN/PRN
D
CLRN/PRN
ENA
ENA
Mercury Programmable Logic Device Family Data Sheet
Figure 28
Q
Q
0
1
Drive Strength Control
shows the IOE configured for DDR
Open-Drain Output
Propagation Delay
Slew Control
Output
VCCIO
VCCIO
Optional
PCI Clamp
Bus-Hold
Circuit
Programmable
Pull-Up
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