ep1m120 Altera Corporation, ep1m120 Datasheet - Page 79

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ep1m120

Manufacturer Part Number
ep1m120
Description
Programmable Logic Device Family
Manufacturer
Altera Corporation
Datasheet

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Altera Corporation
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Drive strength is programmable according to values in
(11) For more information on termination, see
(12) V
(13) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
Timing Model
See the
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.1 V for input
currents less than 100 mA and periods shorter than 20 ns.
Maximum V
V
parentheses.
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V
powered.
Typical values are for T
These values are specified under the Mercury Device Recommended Operating Conditions shown in
page
Input pins are grounded. In the test design, internal logic does not toggle. The test design does not use PLL or HSDI
circuitry. All ESBs are in power-down mode.
Pin pull-up resistance values will lower if an external source drives the pin higher than V
AN 159: Using HSDI in Source-Synchronous Mode in Mercury
accuracy is within 5%.
CCIO
REF
Tables 20
3.
specifies the center point of the switching range.
maximum and minimum conditions for LVPECL, LVDS, RapidIO, and 3.3-V PCML are shown in
Operating Requirements for Altera Devices Data
CC
– 43.:
rise time is 100 ms, and V
A
= 25 C, V
The high-performance multi-level FastTrack Interconnect routing
resources ensure predictable performance, accurate simulation, and
accurate timing analysis. The predictable performance of Mercury devices
offer an advantage over FPGAs, which use a segmented connection
scheme and therefore have unpredictable performance.
Figure 36
registers are within the IOE.
Figure 36. Synchronous Bidirectional Pin External Timing Model
Dedicated
Clock
CCINT
shows the timing model for bidirectional IOE pin timing. All
CC
= 1.8 V, and V
AN 134: Using Programmable I/O Standards in Mercury Devices
must rise monotonically.
Mercury Programmable Logic Device Family Data Sheet
Sheet.
Table 11 on page
CCIO
Devices.
= 1.8 V, 2.5 V, and 3.3 V.
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
53.
t
OUTCOBIDIR
t
t
XZBIDIR
ZXBIDIR
CCINT
CCIO
.
and V
t
t
INHBIDIR
INSUBIDIR
Bidirectional
Pin
CCIO
Table 3 on
or
are
79
13

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