ak4556 AKM Semiconductor, Inc., ak4556 Datasheet
ak4556
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ak4556 Summary of contents
Page 1
... The AK4556 is a low voltage 24bit 192kHz CODEC for high performance battery powered digital audio subsystems. The dynamic performance to power supply voltage ratio is very high, attaining 103dB and 106dB SNR for ADC and DAC, respectively. Sampling rates up to 216kHz are supported. The AK4556 reduces jitter sensitivity by using an integrated switched-capacitor filter. The analog inputs and outputs are single-ended to minimize pin count and external filtering requirements ...
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... Speed) 16TSSOP - 2 - [AK4556] Clock MCLK Divider LRCK BCLK SDTO Serial I/O Interface SDTI CKS3 CKS2 CKS1 CKS0 DEM0 DEM1 AK4556 216kHz 1Hz @ fs = 48kHz Yes 0 91dB 103dB 68dB 28kHz 18/fs 0 5kΩ 90dB 106dB 54dB 21/fs 256/384fs @ Double Speed 128/192fs @ Quad Speed No Master / Slave ...
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... ASAHI KASEI 2. Pin Layout RIN LIN VSS VA AK4552 VD DEM0 DEM1 SDTO CKS0 CSK1 MS0559-E- ROUT 2 19 LOUT VCOM 3 18 PDN 4 17 Top View BCLK 5 16 MCLK 6 15 LRCK 7 14 SDTI CKS3 10 11 CSK2 - 3 - [AK4556] AK4556 2006/11 ...
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... ASAHI KASEI Ordering Guide AK4556VT AKD4556 Pin Layout RIN LIN VSS VA VD DEM0 DEM1 SDTO CKS0 CSK1 MS0559-E-00 -40 ∼ +85°C 20pin TSSOP (0.65mm pitch) Evaluation Board for AK4556 Top View [AK4556] ...
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... When PDN pin is “L”, BCLK pin outputs “L” in master mode. Power-Down & Reset Mode Pin “L”: Power-down and Reset, “H”: Normal operation The AK4556 should be reset once by bringing PDN pin = “L”. Common Voltage Output Pin, 0 Lch Analog Output Pin When PDN pin is “ ...
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... MS0559-E-00 ABSOLUTE MAXIMUM RATINGS Symbol min VA -0.3 VD -0.3 IIN - VINA -0.3 VIND -0.3 Ta -40 Tstg -65 Symbol min VA 2 Symbol min VA 2 [AK4556] max Units 4.6 V 4.6 V ±10 mA VA+0.3 V VD+0.3 V °C 85 °C 150 typ max Units 3.0 3.6 V 3.0 3 0.3 V typ max Units 3.0 3.6 V 3.0 3 ...
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... Units - 24 Bits 2.1 2.3 Vpp 103 - dB 103 - kΩ 110 - dB 0.1 0.5 dB 100 - ppm/°C ...
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... Symbol min typ 20 ∆ 1 24 ∆ -0 [AK4556] max Units µA 10 100 max Units 18.9 kHz - kHz - kHz - kHz ±0. µ 1/ 21.8 kHz - kHz - kHz ±0. µ 1/fs ...
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... Symbol min typ 57.0 - 90.3 SB 112 - ∆ 4 96.0 SB 104 ∆ -0 [AK4556] max Units 37.8 kHz - kHz - kHz - kHz ±0. µ 1/ 43.6 kHz - kHz - kHz ±0. µ 1/ max Units 56.6 kHz - kHz - kHz - kHz ±0. µs ...
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... VA, VD=2.4 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-100µA) Low-Level Output Voltage (Iout=100µA) Input Leakage Current MS0559-E-00 DC CHARACTERISTICS Symbol min VIH 70%VD VIL - VOH VD-0.5 VOL - Iin - - 10 - [AK4556] typ max Units - - V - 30% 0.5 V ± 10 µA - 2006/11 ...
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... S mode) tDLR - tBSD - tSDH 20 tSDS 20 tBCK 1/128fs tBCK 1/64fs tBCKL 33 tBCKH 33 (Note 14) tLRB 20 (Note 14) tBLR mode) tDLR - tBSD - tSDH 13 tSDS [AK4556] typ max Units - 27.648 MHz - 36.864 MHz - - kHz - 48 kHz - 108 kHz - 96 kHz - 216 kHz ...
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... Double Speed Quad Speed Master Mode Normal Speed Double Speed Quad Speed Note 15. The AK4556 can be reset by bringing the PDN pin = “L”. Note 16. This cycle is the number of LRCK rising edges from the PDN pin = “H”. Timing Diagram MCLK LRCK BCLK ...
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... Figure 3. Audio Data Input/Output Timing (Slave) LRCK BCLK tDLR SDTO SDTI Figure 4. Audio Data Input/Output Timing (Master) PDN SDTO MS0559-E-00 tLRB tSDS tSDH tLRB tSDS tSDH tPW tPWV Figure 5. Reset Timing - 13 - [AK4556] VIH VIL VIH VIL tDBS 50%VD VIH VIL 50%VD 50%VD tBSD 50%VD VIH VIL VIL 50%VD 2006/11 ...
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... AK4556 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4556 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be provided unless the PDN pin = “L”. ...
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... Master 128fs (Quad Speed Master 256fs (Normal Speed) Table 3. Mode Setting 2 S mode. SDTI LRCK 24bit, MSB justified H/L 2 24bit Compatible L/H 24bit, LSB justified H/L Table 4. Audio Interface Format - 15 - [AK4556] Audio Interface MCLK Format (See ) Table 4 LJ/RJ LJ/RJ LJ/RJ LJ/ ...
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... Don’t Care Figure 8. Mode LJ/RJ Timing DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 5. De-emphasis filter control - 16 - [AK4556 Don’t Care Rch Data 3 ...
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... LOUT/ROUT pins become Hi-Z at power-down. (4) In master mode, LRCK and BICK output “L” at power-down. MS0559-E-00 (1) Power-down Init Cycle Normal Operation Power-down “0”data “0”data GD (2) (2) (3) (4) The clocks may be stopped. Mute ON Figure 9. Power-up/down Sequence - 17 - [AK4556] Normal Operation GD Idle Noise GD 2006/11 ...
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... S, it starts clocking on the falling edge of BCLK after the first rising edge of BCLK after the falling edge of LRCK. The AK4556 is in power down state until LRCK is input. In master mode, reset and power down states are released by MCLK. The internal timing also starts by MCLK. ...
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... Figure 10. System Connection Diagram Example (Mode 0: AK4552 Compatible Mode) Notes: - VSS of the AK4556 should be distributed separately from the ground external digital devices not allow digital input pins to float. - When LOUT/ROUT drives some capacitive load, a 220Ω resistor should be added in series between LOUT/ROUT and capacitive load ...
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... VD pin is supplied from VA pin via 5.1Ω. Alternatively if VA and VD pins are supplied separately, the power up sequence is not critical. VSS pin of the AK4556 should be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board ...
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... ASAHI KASEI 20 1 0.65 0.195 ~ 0.275 0.10 Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0559-E-00 PACKAGE 6.5 ± 0.1 0.105 ~ 0.175 Epoxy Cu Solder (Pb free) plate - 21 - [AK4556 2006/11 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Rev.0.4 AKM CONFIDENTIAL MARKING AKM 4556VT XXXXXX 1) Pin #1 indication 2) Date Code: XXXXXX (6 digits) 3) Marketing Code: 4556VT Revision History Reason Page Contents First Edition IMPORTANT NOTICE - 22 - [AK4556] 2005/12 ...