ak4556 AKM Semiconductor, Inc., ak4556 Datasheet - Page 14

• Manufacturer Part Number: ak4556
• Description: 3v 192khz 24bit ?? Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MCLK, BCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, BCLK frequency, HPF (ON or OFF) and master/slave are selected by CKS3-0 pins
as shown in Table 3. When MCLK is 192fs, 384fs or 768fs, the sampling frequency does not support variable pitch (Table
2).
All external clocks (MCLK, BCLK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not
provided, the AK4556 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK4556 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless the PDN pin = “L”.
MS0559-E-00
44.1kHz
192kHz
32kHz
48kHz
96kHz
System Clock
fs
24.576MHz
128fs
N/A
N/A
N/A
N/A
Normal Speed
Double Speed
Quad Speed
36.864MHz
Mode
Table 1. System Clock Example (N/A: Not Available)
192fs
N/A
N/A
N/A
N/A
Table 2. Sampling Frequency Range
OPERATION OVERVIEW
11.2896MHz
12.288MHz
24.576MHz
108kHz < fs ≤ 216kHz
8.192MHz
54kHz < fs ≤ 108kHz
96kHz < fs ≤ 192kHz
Sampling Frequency
8kHz ≤ fs ≤ 48kkHz
48kHz < fs ≤ 96kHz
8kHz ≤ fs ≤ 54kHz
256fs
N/A
- 14 -
MCLK
16.9344MHz
12.288MHz
18.432MHz
36.864MHz
384fs
N/A
256fs/512fs
384fs/768fs
MCLK
256fs
384fs
128fs
192fs
22.5792MHz
16.384MHz
24.576MHz
512fs
N/A
N/A
33.8688MHz
24.576MHz
36.864MHz
768fs
N/A
N/A
[AK4556]
2006/11