ak4556 AKM Semiconductor, Inc., ak4556 Datasheet - Page 17

• Manufacturer Part Number: ak4556
• Description: 3v 192khz 24bit ?? Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The ADC has a Digital High Pass Filter (HPF) for DC-offset cancellation. The cut-off frequency of the HPF is 1Hz at
fs=48kHz and the frequency response at 20Hz is -0.12dB. It also scales with the sampling frequency (fs). The HPF is
controlled by CKS3-0 pins (Table 3). If the HPF setting (ON/OFF) is changed at operating, click noise occurs by
changing DC offset.
The ADC and DAC are placed in power-down mode by bringing the PDN pin = “L”, and each digital filter is also reset at
the same time. These resets should always be done after power-up. For the ADC, an analog initialization cycle starts after
exiting the power-down mode. The output data, (SDTO) becomes available after 4131 cycles (@ Normal Speed) of
LRCK in master mode or 4134 cycles (@ Normal Speed) of LRCK in slave mode. During initialization, the ADC digital
data outputs of both channels are forced to a 2’s complement “0”. The ADC output data settles and correlates to the input
signal after the end of initialization (settling time is approximately equal to the group delay time.) The initialization cycle
does not affect the DAC operation.
Notes:
MS0559-E-00
Digital High Pass Filter
Power-down & Reset
Clock In
MCLK,LRCK,BCLK
DAC Internal
DAC In
DAC Out
ADC Internal
ADC In
ADC Out
External
PDN
(1) Slave mode (typ): 4134/fs @ Normal Speed, 8262/fs @ Double Speed, 16518/fs @ Quad Speed
(2) Click noise occurs at the “↑↓” of PDN signal. Mute the analog output externally if the click noise influences
(3) LOUT/ROUT pins become Hi-Z at power-down.
(4) In master mode, LRCK and BICK output “L” at power-down.
(Digital)
(Analog)
(Analog)
(Digital)
Mute
State
State
Master mode (typ): 4131/fs @ Normal Speed, 8259/fs @ Double Speed, 16515/fs @ Quad Speed
system performance.
Normal Operation
Normal Operation
Idle Noise
GD
GD
Figure 9. Power-up/down Sequence
(2)
Power-down
Mute ON
Power-down
(4)
(3)
The clocks may be stopped.
- 17 -
(2)
“0”data
“0”data
Normal Operation
Init Cycle
(1)
GD
Idle Noise
Normal Operation
GD
[AK4556]
2006/11