ak4538 AKM Semiconductor, Inc., ak4538 Datasheet - Page 21

• Manufacturer Part Number: ak4538
• Description: 16bit ?? Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

(2) External mode (PMPLL bit = “0”)
When the PMPLL bit = “0”, the AK4538 works in external clock mode. The MCKO pin outputs a buffered clock of MCKI
input.
For example, when MCKI = 256fs, the sampling frequency is changeable from 7kHz to 48kHz (Table 7).
The MCKO bit controls MCKO output enable. The frequency of MCKO is selectable via register the PS1-0 bits as defined
in Table 8. If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be
changed after LRCK is input in slave mode. The master clock frequency should be changed only when both the
PMADC and PMDAC bits = “0”.
LRCK and BICK are output from the AK4538 in master mode. The clock to the MCKI pin must not stop during normal
operation (PMPLL bit = “1”). If this clock is not provided, the AK4538 may draw excess current due to its use of internal
dynamically refreshed logic. If the external clocks are not present, place the AK4538 in power-down mode (PMADC bit =
PMDAC bit = “0”).
MCKI, BICK and LRCK clocks are required in slave mode. The master clock (MCKI) should be synchronized with
sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK should always be present
whenever the AK4538 is in normal operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided,
the AK4538 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK4538 in power-down mode (PMADC bit = PMDAC bit = “0”).
MS0198-E-01
MCKI pin
MCKO pin
BICK pin
LRCK pin
MCKI pin
MCKO pin
BICK pin
LRCK pin
Mode
0
1
2
3
Power up
Frequency set by PLL1-0
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
Input
Input
Power up
Frequency set by PLL1-0
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
BF bit = “0” : 64fs Output
BF bit = “1” : 32fs Output
Output
FS1
0
0
1
1
Table 5. Clock Operation at Master Mode (PLL Mode)
Table 6. Clock Operation at Slave Mode (PLL Mode)
Table 7. Sampling Frequency Select (EXT Mode)
FS0
0
1
0
1
Master Mode (M/S pin = “H”)
Power down
Fixed to “L” or “H” externally
Fixed to “L” or “H” externally
Slave Mode (M/S pin = “L”)
Power down
Refer to Table 1
- 21 -
Sampling Frequency (fs)
Refer to Table 1
7kHz 48kHz
7kHz 24kHz
7kHz 12kHz
7kHz 48kHz
“L”
“L”
“L”
“L”
PLL Unlock
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
PLL Unlock
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
1024fs
MCKI
256fs
512fs
256fs
“L”
“L”
Input
Input
Default
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