ak4538 AKM Semiconductor, Inc., ak4538 Datasheet - Page 53

• Manufacturer Part Number: ak4538
• Description: 16bit ?? Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0198-E-01
Addr
09H
LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 30)
RATT: ALC1 Recovery GAIN Step (see Table 31)
LMAT1-0: ALC1 Limiter ATT Step (see Table 32)
ZELM: Enable zero crossing detection at ALC1 Limiter operation
ALC1: ALC1 Enable Flag
ALC2: ALC2 Enable Flag
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about 2dB.
Default is “0”.
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For example,
when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the ALC1 recovery
operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF6-0 bits), the IPGA value does not increase.
During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by LMTH,
the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value is
47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter operation starts, resulting
in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = “00”
( 8dB), it clips to “00”.
0: Enable (Default)
1: Disable
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently and the
IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery
operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
0: ALC1 Disable (Default)
1: ALC1 Enable
0: ALC2 Disable
1: ALC2 Enable (Default)
LMTH
Register Name
ALC Mode Control 1
0
1
Default
R/W
Table 30. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
ALC1 Limiter Detection Level
ADC Input
ADC Input
LMAT1
6.0dBFS
4.0dBFS
0
0
1
1
Table 31. ALC1 Recovery Gain Step Setting
Table 32. ALC1 Limiter ATT Step Setting
RD
D7
0
0
RATT
0
1
LMAT0
ALC2
R/W
0
1
0
1
D6
1
GAIN STEP
ALC1 Recovery Waiting Counter Reset Level
- 53 -
ALC1
1
2
R/W
ATT STEP
6.0dBFS
4.0dBFS
D5
0
1
2
3
4
ZELM
R/W
D4
0
ADC Input
ADC Input
Default
Default
LMAT1
R/W
D3
0
8.0dBFS
6.0dBFS
LMAT0
R/W
D2
0
RATT
R/W
D1
0
Default
[AK4538]
LMTH
R/W
2003/5
D0
0