ml7051la Oki Semiconductor, ml7051la Datasheet - Page 15
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ml7051la
Manufacturer Part Number
ml7051la
Description
Bluetooth Baseband Controller Ic
Manufacturer
Oki Semiconductor
Datasheet
1.ML7051LA.pdf
(24 pages)
External Memory
Note: Oki software settings:
Note: A device with an access time of 120 nsec or less is recommended.
1 Semiconductor
ML7051LA specifications for the devices that are connected to MCS[0] and MCS[1] are explained below.
When connected to MCS[0] device:
- 1 memory bank
- Bus width: 8 or 16 bits
- Byte access control: BS/WE
- Supported devices:
Normal SRAM, Flash Memory, Page mode Flash memory
MCSn0
- Insert the maximum wait immediately after reset.
- Page mode: OFF
- During operation (32 MHz operation),
MBSn*
MWEn
MREn
XA
XD_O
(write)
(read)
[*1]
[*2]
Access time: 3 clock cycles
Data OFF time: 1 clock cycle
XD_I
Access time:
3, 4, 5, 6, 7, 8 clock cycles (including one clock cycle for set-up)
6, 8, 10, 12, 14, 16 clock cycles (including two clock cycles for set-up)
Data OFF time:
1, 2, 3, 4 clock cycles
clocks
1 or 2
[*1]
Bus timing to MCS[0] device
[*2]
1 or 2 clocks
[*1]
1 clock fixed
FEDL7051LA-02
ML7051LA
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