ml7051la Oki Semiconductor, ml7051la Datasheet - Page 7
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ml7051la
Manufacturer Part Number
ml7051la
Description
Bluetooth Baseband Controller Ic
Manufacturer
Oki Semiconductor
Datasheet
1.ML7051LA.pdf
(24 pages)
µPLAT_SIO I/F
GPIO I/F
JTAG I/F
PCM I/F
1 Semiconductor
[*3]
GPIO[15:0]
PCMSYNC
Pin Name
Pin Name
Pin Name
Pin Name
PCMOUT
PCMCLK
nTRST
PCMIN
URXD
UTXD
TDO
TMS
TCK
TDI
CIO15: B2
CIO14: A2
CIO13: B1
CIO12: C3
CIO11: C1
CIO10: D3
CIO9: E3
CIO8: D2
CIO7: E1
CIO6: E4
CIO5: E2
CIO4: F1
CIO3: F2
CIO2: F4
CIO1: F3
CIO0: G3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
Pull Up/Down
Pull Up/Down
Pull Up/Down
Pull Up/Down
GPIO15/SOUT (UART I/F)
GPIO14/SIN (UART I/F)
GPIO13/DCD (UART I/F)
GPIO12/RTS (UART I/F)
GPIO11/CTS (UART I/F)
GPIO10/DSR (UART I/F)
GPIO9/DTR (UART I/F)
GPIO8/RI (UART I/F)
GPIO7/STXD (SIO I/F)
GPIO6/SRXD (SIO I/F)
GPIO5/STXDCLK (SIIO I/F)
GPIO4/SRXDCLK (SIO I/F)
GPIO3/UTXD (UPLAT_SIO I/F)
GPIO2/URXD (UPLAT_SIO I/F)
GPIO1/NWAIT (Memory I/F)
GPIO0/VBUS (USB I/F)
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Internal
Internal
Internal
Internal
—
—
—
—
—
Value
Value
Value
Value
Initial
Initial
Initial
Initial
—
—
—
—
—
—
—
—
—
H
L
L
Placement
Placement
Placement
Placement
B12
L12
K12
Pin
Pin
[*3]
J11
J13
Pin
Pin
D4
A3
A4
C4
F2
F4
PCM data output
PCM data input
PCM sync signal (8 kHz), in the input state
after initialization (can be switched by an
internal register)
PCM clock (64 kHz/128 kHz), in the input
state after initialization (can be switched by an
internal register)
Parallel I/O data (in the input state after
initialization)
Serial data output (Pin shared with GPIO3)
Serial data input (Pin shared with GPIO2)
Serial data input
Serial data output
Reset pin
Mode setting pin
Serial data clock
Description
Description
Description
Description
FEDL7051LA-02
ML7051LA
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