ml7019 ETC-unknow, ml7019 Datasheet
ml7019
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ml7019 Summary of contents
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... The ML7019 is best suited for line card applications with easy interface to subscriber line interface circuits (SLICs). The SLIC interface latches are embedded onto this CODEC, thus eliminating the need for external components and optimizing board space ...
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... ML7019 v FUNCTIONAL BLOCK DIAGRAM RC AIN1 - + LPF GSX1 RC AIN2 - + LPF GSX2 - AOUT1 + - AOUT2 + SG SGC GEN VDD PIN ASSIGNMENT ML7019MA SGC 1 AOUT2 AOUT1 4 VDD C1A 7 C2A 8 C3A 9 ALAW 10 RSYNC 11 DIN 12 8th BPF AD CONV. 8th BPF AUTO ZERO 5th S&H LPF DA CONV ...
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... ML7019 v PIN DESCRIPTION AIN1, AIN2, GSX1, GSX2 AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2. GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2. AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the op-amp and are used to adjust the level, as shown below ...
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... ML7019 VDD Power supply for +5V. A power supply for an analog circuit of the system which the device is applied should be used a bypass capacitor of 0.1 F with excellent high frequency characteristics and a capacitor should be connected between this pin and the AG pin if needed. ...
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... ML7019 XSYNC Transmit synchronizing signal input. The PCM output signal from the DOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with the BCLK. The frequency should be 8KHz 50ppm to guarantee the AC characteristics which are mainly the frequency characteristic of the transmit section ...
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... ML7019 DOUT DOUT is a data output pin. Signal which consist of a total 28 bits configured by the voice band PCM signal(16 bits for 2CH), the echo bit(6 bits for latch signal and 2 bits for power down state indication), and empty bit(4 bits), The output signal is output from CH1's MSD bit in a sequential order, synchronizing with the rising edge of the BCLK signal ...
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... ML7019 C1A, C2A, C3A, C1B, C2B, C3B General-purpose Latched output signal. C1A, C2A, C3A, C1B, C2B, C3B bits of DIN are latched at internal timing. These outputs can drive a LSTTL/CMOS device without external resistor. 7 ...
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... ML7019 v ABSOLUTE MAXIMUM RATING Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Operating Temperature Storage Temperature Symbol Conditions - V DD AG=0V, DG=0V V AIN AG=0V, DG=0V V DIN - STG Ratings Unit - 0 150 8 ...
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... ML7019 v RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Analog Input Voltage Digital Input High Voltage Digital Input Low Voltage Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse ...
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... ML7019 v ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics Parameter Power Supply Current Input High Voltage Input Low Voltage High Level Input leakage current Low Level Input leakage current Digital Output low voltage Digital Output High Voltage Digital Output leakage current Input capacitance ...
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... ML7019 Receive Analog interface Characteristics Parameter Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage V Symbol Conditions AOUT1, AOUT2 (each) R LAO With respect to SG AOUT1, AOUT2 C LAO AOUT1, AOUT2,RL=0.6K V OAO With respect to SG AIN1, AIN2 V OSAO With respect to SG =5V 5%, Ta= -40 ...
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... ML7019 AC Characteristics Parameter Symbol Transmit Loss T1 Frequency Response Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Receive Loss R1 Frequency Response Loss R2 Loss R3 Loss R4 Loss R5 Transmit SDT1 Signal to Distortion SDT2 Ratio SDT3 SDT4 SDT5 Receive SDR1 Signal to Distortion SDR2 Ratio SDR3 SDR4 SDR5 Transmit GTT1 ...
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... ML7019 AC Characteristics (Continued) Parameter Symbol NIDLET Idle channel noise NIDLER AVT Absolute level (Initial Difference) AVR Absolute level AVTt ( Deviation of Temp- AVRt erature and Power) Absolute Delay T D Tgd T1 Transmit group Tgd T2 delay Tgd T3 Tgd T4 Tgd T5 Tgd R1 Receive group Tgd R2 delay ...
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... ML7019 AC Characteristics (Continued) Parameter Symbol Discrimination DIS Out of band S spurious Intermodulation IMD Distortion Power Supply PSRT Noise Rejection PSRR Ratio Digital output Tsd delay time Txd1 Txd2 Txd3 TpdC *4 The measurement under idle channel noise V DD Conditions freq. level (Hz) (dBmO) 4. ...
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... ML7019 v TIMING DIAGRAM TRANSMIT SIDE BCLK 1 TXS TSX XSYNC TXD1 TSD DOUT MSD RECEIVE SIDE BCLK 1 TRS TSR RSYNC DIN1 MSD DIN2 TRANSMIT SIDE 1 BCLK XSYNC DOUT MSD CH1PCM DATA RECEIVE SIDE 1 BCLK RSYNC DIN M SDD2 ...
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... ML7019 BCLK XSYNC RSYNC CH1 P CM Control CH2 PUT DATA DATA IN PUT DATA DIN ...
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... ML7019 v Application circuit Ch1 analog input Ch1 analog output Ch2 analog input Ch2 analog output + RECOMMENDATIONS FOR ACTUAL DESIGN To assure electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins ...