ml7019 ETC-unknow, ml7019 Datasheet - Page 5

• Manufacturer Part Number: ml7019
• Description: Single Rail Dual Channel Codec
• Manufacturer: ETC-unknow

l ML7019
XSYNC
DIN
Transmit synchronizing signal input.
The PCM output signal from the DOUT pin is output in synchronization with this
transmit synchronizing signal. This synchronizing signal triggers the PLL and
synchronizes all timing signals of the transmit section. This synchronizing signal
must be synchronized in phase with the BCLK. The frequency should be 8KHz
50ppm to guarantee the AC characteristics which are mainly the frequency
characteristic of the transmit section.
However, if the frequency characteristic of the system used is not strictly specified,
this device can operate in the range of 6KHz to 9KHz, but the electrical
characteristics in this specifications are not guaranteed.
Setting this signal to logic "1" or "0" drives both CH1 and CH2 circuits to power
saving state.
DIN is a data input pin.
Signals which consist of a total 28 bits configured by the voice band PCM signal(16
bits for 2CH), the general-purpose latch signal(6 bits for both channel), the power
down control signal for each channel(2 bits) and empty bit(4 bits),
The signal is shifted at a falling edge of the BCLK signal and latched into the
internal register when shifted by 28 bits.
The voice band signal is converted to an analog signal in synchronization with the
RSYNC signal and BCLK. The analog signal of channel 1 is output from AOUT1
pin and the analog signal of channel 2 is output from AOUT2 pin.
The general purpose latch signal(C3A,C2A,C1A,C3B,C2B,C1B) are output from
six latch output pins.
When the PD1 bit of DIN is at logic "0" level, CH1 block is in a power down state.
When the PD2 bit of DIN is at logic "0" level, CH2 block is in a power down state.
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