ml7037 Oki Semiconductor, ml7037 Datasheet - Page 10

• Manufacturer Part Number: ml7037
• Description: Ml7037-003 Dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free
• Manufacturer: Oki Semiconductor

Not for Publication
GPIB1 ( LINEEN)
This is a general-purpose input port pin.
This also works as a power-down control over the line-side analog interface as the secondary function.
When this pin is logic ‘0’, the line-side analog interface is enabled; and, when this pin is logic ‘1’, the line-side
analog interface is powered-down (excluding the LVFRO output amp).
During power-down, the LVFRO outputs 1.4V approx..
When the MCUSEL pin is logic ‘1’, this pin is automatically assigned with its secondary function.
When the MCUSEL pin is logic ‘0’, this pin’s function assignment follows the state of GPFB1-bit [GPCR1-B1].
(Note) The change of the input state to this pin is detected at the rising edge of the SYNC clock so that the change
(Note) In an application where the line-side codec is never enabled, the LINN pin and the LGSX pin must be
(Note) The change of the enabled/disabled state of the line-side codec must be made during power-down state
GPIB2 (VFROSEL)
This is a general-purpose input port pin.
This also works as the output state control over the AVFRO pin and the LVFRO pin as the secondary function.
When this pin is logic ‘0’, they output the AVREF level (1.4V apporx.); and, when this pin is logic ‘1’, they output
speech signals.
When the MCUSEL pin is logic ‘1’, this pin is automatically assigned with its secondary function.
When the MCUSEL pin is logic ‘0’, this pin’s function assignment follows the state of GPFB2-bit [GPCR1-B2].
(Note) When, during a call, the output state is changed or the reset is made, minor noises could happen due to an
(Note) The power-down execution and its release are recommended to be made when the AVFRO pin and the
(Note) When this pin is not used, set this pin to logic ‘0’.
MCK/X1, XO
These are pins to connect a crystal unit, and the former is used as the master clock input pin as well. The clock
frequency is 12.288 MHz.
During power-down mode (PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’), oscillation of the connected
crystal unit is stopped.
After the release of the power-down, the connected crystal unit starts being oscillated, but the master clocks start
being utilized within this LSI only after the steady oscillation waiting time (28ms approx.).
Refer to Figure 4 for an example application with an external clock and that with a crystal unit.
(Note) When a crystal unit is used, connect the unit and a feedback resistor of 1M (R) between the MCK/XI
OKI Semiconductor
ex) External Clock
MCK/XI
of the input state to this pin less than 250 s may not be reflected as the LSI behavior.
shorted.
(PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) or during initial mode.
interruption at an arbitrary point in a sequence of PCM codes so that this output state selection and the
reset are recommended to be made before a call as long as it is application-wise allowed.
LVFRO pin are selected to output the AVREF level.
and the XO. The appropriate values of capacitors (C1, C2) to be connected between the MCK/XI and
GND and between the XO and GND are influenced by load capacitance of a crystal unit and PCB patterns
so that they are recommended to be determined by asking a crystal unit vendor for a matching test.
12.288MHz
Floating
XO
Figure 4 Examples of external clock and crystal unit as a master clock
C1
MCK/XI
ex) Crystal Unit
X'tal
R
XO
C2
(12.288MHz)
HC-49/U-S
X’tal
PEDL7037-003-05Zz_Digest
1M
R
ML7037-003
10pF
C1
10/41
10pF
C2