msm7580 Oki Semiconductor, msm7580 Datasheet
msm7580
Available stocks
Related parts for msm7580
msm7580 Summary of contents
Page 1
... MSM7580 ITU-T G.721 ADPCM TRANSCODER GENERAL DESCRIPTION The MSM7580 is an ADPCM transcoder which is used by the new digital cordless system. It converts 64 kbps voice PCM serial data to 32 kbps ITU-T G.721 ADPCM serial data, and vice versa. This device consists of two systems with full-duplex voice data channels and a data-through mode ...
Page 2
BCLKP MUTE1 CODER SIP1 S P SYNCP1 DECODER MUTE / SOP1 S P PAD LAW THR1 THR2 CODER SIP2 S P SYNCP2 MUTE / DECODER SOP2 PAD S P MUTE2 PDN1 PDN2 BCLKA POWER DOWN CODER P S CODER DECODER ...
Page 3
... PAD/MUTE BCLKP GND LAW SYNCP1 MUTE1 THR1 SOP1 SIP1 28-Pin Plastic SOP MSM7580 SOA2 SIA2 SYNCA2 RES2 DET2 PDN2 V DD BCLKA PDN1 DET1 RES1 SYNCA1 SIA1 SOA1 3 ...
Page 4
... ADPCM input data, when the MUTE mode is selected by the PAD/MUTE pin. When the PAD mode is selected, the PCM output has loss. Normally, these pins are set to a digital "0". When the data through mode is selected, the function of these pins is invalid. MSM7580 4 ...
Page 5
... When the data-through mode is selected, SOA1 enters to the high impedance state after outputting an 8-bit serial data stream. SIA2, SOA2 ADPCM serial data input (SIA2) and output (SOA2) pins for Channel 2. These pins function the same as SIA1 and SOA1. MSM7580 5 ...
Page 6
... Bit clock input pin used to define the data transmission speed at the ADPCM interface. This pin can be used for Channels 1 and 2, which allows the ADPCM data interface speed to be defined differently than the PCM data interface speed Power supply. The device must operate 10%. MSM7580 6 ...
Page 7
... BCLKA, BCLKP to SYNCP SYNCP to BCLKA, BCLKP BCLKA, BCLKP to SYNCA SYNCA to BCLKA, BCLKP SYNCP1, SYNCP2, SYNCA1, SYNCA2 — — SOP1, SOP2, SOA1, SOA2 DL (Pull-up Resistor) SOP1, SOP2, SOA1, SOA2, DET1, DET2 MSM7580 Rating Unit –0 0 –55 to +150 °C Min. Typ. ...
Page 8
... — I DET1, DET2 : I = –0 LSTTL, Pull-up : 500 W 0.0 DET1, DET2 : I = 1.6 mA 0.0 OL SOP1, SOP2, SOA1, SOA2 — — — Condition Min. 1 LSTTL + 100 pF Pull-up: 500 W MSM7580 Typ Max. Unit 0.1 0.2 mA — — 0.6 V — 2.0 mA — 0.5 mA — ...
Page 9
... DD1 Note: 4-bit data pattern except "0000" XD2 t XD3 LSB LSB RD2 "0000" MSM7580 LSB RD3 LSB Note) t DD2 9 ...
Page 10
... Even if BCLK is not 128 kHz, these processings are performed in the absolute time counted from the rising edge of SYNCA. Therefore, MUTE1 and MUTE 2 pins must be controlled cover there processsings. 78.125ms PAD/MUTE="H" LSB 12dB loss transmit data PAD/MUTE="L" LSB MUTE (idle channel state) MSM7580 0dB transmit data 0dB transmit data 10 ...
Page 11
... Through-data Output (SOA) BCLKA THR Note: That data-ship may occur when the rising edge (data load point) of SYNCA and input of the internal latch timing overlap each other. Through-data 8b ADPCM Latch CODER Latch timing=A LSB MSM7580 SYNCA Parallel S E SOA L Serial BCLKA 4b Through-data MSB ...
Page 12
... PCM side SYNC (SYNCP) Throgh-data output (SOP) BCLKP THR Less than are BCLKP cycle from the rising edge of SYNCA signal. Through-data 8b 8 ADPCM Latch DECODER Latch timing=A LSB MSM7580 SYNCP Parallel S E SOP L Serial BCLKP 8b Through-data This data is output here. MSB 100ns or more ...
Page 13
... MUTE2 SYNCP2 DET2 PDN2 PAD/MUTE BCLKP V DD GND BCLKA PDN1 LAW SYNCP1 DET1 RES1 MUTE1 THR1 SYNCA1 SOP1 SIA1 SIP1 SOA1 – GND MSM7580 V DD CODER2 ADPCM Output DECODER2 ADPCM Input V DD DECODER1 ADPCM Input CODER1 ADPCM Output 13 ...
Page 14
... Data slip means that data is deleted or the same data is output twice PCMDATA2 ADPCMDATA1 ADPCMDATA0 *t1 is the falling edge of the 8th BCLK counted from t0 ADPCMDATA2 PCMDATA1 PCMDATA0 *t1 is the falling edge of the 8th BCLK counted from t0. MSM7580 PCMDATA3 ADPCMDATA2 ADPCMDATA1 ADPCMDATA3 PCMDATA2 PCMDATA1 14 ...
Page 15
... PLL (4) (6) 8bit 8bit Latch Latch From To DECODER DECODER SYNCA MSM7580 * t4 is the falling edge of the 8th BCLK counted from the rising edge of SYNCP MSB LSB * t4 is the falling edge of the 8th BCLK t5 counted from the rising edge of SYNCP. MSB LSB * t5 is the rising edge of SYNCA ...
Page 16
... Therefore, the timings of SYNC signals of both PCM and ADPCM sides should not be set up in the range about 500nsec of Tsip=t1, Tsia=t3 and Tsop=t2. For normal operation, SYNC clocks for ADPCM and PCM sides should be continuous at 8 kHz and synchronized with each other even if their phases are different. MSM7580 16 ...
Page 17
... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM7580 (Unit: mm) Package material Epoxy resin ...
Page 18
... REVISION HISTORY Document Date No. E2U0031-39-61 Jun. 1999 FEDL7580-04 Aug. 12, 2004 Page Previous Current Edition Edition — — Final edition 3 — — Final edition 4 Modified Sections (a), CODER Timing Diagram and (b), DECODER Timing Diagram. MSM7580 Description 18 ...
Page 19
... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd. MSM7580 19 ...