tea5761uk NXP Semiconductors, tea5761uk Datasheet - Page 16

• Manufacturer Part Number: tea5761uk
• Description: Tea5761uk Low-voltage Single Chip Fm-stereo Radio
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13451
Product data sheet
9.2.1 Multiple interrupt events
9.2.2 IF frequency flag
9.2.3 RSSI threshold flag
9.2 Interrupt flags and behavior
If the interrupt mask register bit is set then the setting of an interrupt flag for that bit
causes a hardware interrupt (pin INTX goes LOW). If the event occurs again, before the
flag is cleared, then this does not trigger any further hardware interrupts until that specific
flag is cleared. However, two different events can occur in sequence and generate a
sequence of hardware interrupts. A second interrupt can be generated only after the
INTMSK byte is read, followed by a write as the first interrupt blocks the input of the INTX
one-shot generator.
If subsequent interrupts occur within the INTX LOW period then these do not cause the
INTX period to extend beyond its specified maximum period (see
During automatic frequency search or preset, the FM part of the TEA5761UK performs a
check of the received IF frequency. If an incorrect IF frequency is received, it indicates a
detuning situation or the presence of either strong interferers or tuning to an image which
sets bit IFFLAG in the INTFLAG register. Also a preset to a channel with no signal may
result in a wrong IF count value and hence the setting of bit IFFLAG.
When a search or preset is finished, bit FRRFLAG will be set to indicate this and an
interrupt is generated. The microcontroller can now read the outcome of the registers
which will contain the IF count value and the IFFLAG status of the channel it is tuned to.
15 ms after the FRRFLAG flag has been set the IF counter will start to run continuously on
the tuned frequency and if the conditions for correct frequency are not met then this sets
bit IFFLAG in the interrupt register. When bit IFMSK is set this will also cause an interrupt.
Bit IFFLAG is cleared by reading byte0R, or by starting the tuning algorithm.
The RSSI level voltage reflects the field strength received by the antenna. The voltage
level is analog-to-digital converted to a 4-bit value and output via the I
level value can be compared to a threshold level (see
converts the analog value to digital) can be triggered to convert in two ways:
1. During a tuning step, which can be a search or a preset, it is triggered by these
2. After a search or a preset, the threshold for comparison is switched to the hysteresis
algorithms and compares the level with the threshold set by bits SSL[1:0]. Bit
LEVFLAG is set if the RSSI level drops below the threshold level set by bits SSL[1:0];
see
is set.
level. The hysteresis level is set by the level bits and can be selected using bit LHSW
(see
compares the level each 500 s with this hysteresis level. Bit LEVFLAG is set if the
RSSI level drops below the threshold level set by the LH bits; the hardware interrupt is
only generated if the corresponding mask bit is set. Bit LHSW allows either a small or
a large hysteresis to be selected. When a search or preset is done with the ADC level
set to 3 then when the algorithm has finished, the threshold level is set to 0. Hence the
LEVFLAG will never be set.
Table
Table
15. The hardware interrupt is only generated if the corresponding mask bit
21). Then it waits 15 ms and the level ADC starts to run automatically and
Rev. 01 — 2 August 2006
Low voltage single-chip FM stereo radio
Table
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
21). The level ADC (which
TEA5761UK
Section
2
C-bus. This 4-bit
9.3).
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