tea5761uk NXP Semiconductors, tea5761uk Datasheet - Page 20

• Manufacturer Part Number: tea5761uk
• Description: Tea5761uk Low-voltage Single Chip Fm-stereo Radio
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13451
Product data sheet
Fig 9. Bus timing diagram
ENABLE
BUS
SCL
SDA
t
t
t
t
t
t
Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.
t
t
t
C
t
t
f
r
HD;STA
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
SU;BUSEN
HO;BUSEN
= fall time of both SDA and SCL signals: 20 + 0.1 C
b
= rise time of both SDA and SCL signals: 20 + 0.1 C
= capacitive load of one bus line: < 400 pF.
= bus free time between a STOP and a START condition: > 600 ns.
= HIGH period of the SCL clock: > 600 ns.
P
= setup time for a repeated START condition: > 600 ns.
= data setup time: t
= hold time (repeated) START condition. After this period, the first clock pulse is generated: > 600 ns.
= data hold time: 300 < t
t
= setup time for STOP condition: > 600 ns.
SU;BUSEN
10.3 Register map
= bus enable setup time: t
= bus enable hold time: t
t
BUF
Table 9:
Byte number
Read
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
10R
S
t
HD;STA
SU;DAT
Register overview
HD;DAT
t
> 100 ns. If ASIC is used in a standard mode I
SU;DAT
Write
0W
1W
2W
3W
4W
5W
HO;BUSEN
SU;BUSEN
< 900 ns.
t
HD;DAT
> 10 s.
> 10 s.
Rev. 01 — 2 August 2006
Byte name
INTFLAG
INTMSK
FRQSETMSB
FRQSETLSB
TNCTRL1
TNCTRL2
FRQCHKMSB
FRQCHKLSB
IFCHK
LEVCHK
TESTBITS
b
t
r
t
b
< t
HIGH
< t
f
r
t
< 300 ns, where C
f
< 300 ns, where C
t
LOW
Low voltage single-chip FM stereo radio
Access
R
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
b
b
= total capacitance on bus line in pF.
= total capacitance on bus line in pF.
t
2
SU;STA
C-bus system, t
Sr
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset value Reference
00h
00h
80h
00h
08h
D2h
-
-
-
-
00h
SU;DAT
TEA5761UK
> 250 ns.
t
SU;STO
t
HO;BUSEN
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
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P
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