ml87v2104 Oki Semiconductor, ml87v2104 Datasheet - Page 14

• Manufacturer Part Number: ml87v2104
• Description: Display Controller With Built-in Display Memory And Jpeg
• Manufacturer: Oki Semiconductor

OKI Semiconductor
[Control Registers]
• CPPOL
• HLCYC
• HST1POL
• HST1POS
• HST2POL
• HST2POS
• LDP1POL
• LDP1ST
• LDP1ED
• LDP2POL
• LDP2ST
• LDP2ED
• LDP3POL
• LDP3ST
• LDP3ED
• LDP4POL
• LDP4ST
• LDP4ED
• VFCYC
• FDP1POL
• FDP1ST
• FDP1ED
• FDP2POL
• FDP2ST
• FDP2ED
• FDP3POL
• FDP3ST
• FDP3ED
• FDP2MIX
• FDP3MIX
• ACTHST
• ACTHED
• ACTVST
• ACTVED
: Synchronous polarity selection for CP and output data, 1 bit (write/read)
: HST/LDP cycle (units of the number of CP clocks), 11 bits (write/read)
: HST1 pulse polarity selection, 1 bit (write/read)
: HST1 pulse position, 11 bits (write/read)
: HST2 pulse polarity selection, 1 bits (write/read)
: HST2 pulse position, 11 bits (write/read)
: LDP1 pulse polarity selection, 1 bits (write/read)
: LDP1 pulse's front edge position, 11 bits (write/read)
: LDP1 pulse's rear edge position, 11 bits (write/read)
: LDP2 pulse polarity selection, 1 bits (write/read)
: LDP2 pulse's front edge position, 11 bits (write/read)
: LDP2 pulse's rear edge position, 11 bits (write/read)
: LDP3 pulse polarity selection, 1 bits (write/read)
: LDP3 pulse's front edge position, 11 bits (write/read)
: LDP3 pulse's rear edge position, 11 bits (write/read)
: LDP4 pulse polarity selection, 1 bits (write/read)
: LDP4 pulse's front edge position, 11 bits (write/read)
: LDP4 pulse's rear edge position, 11 bits (write/read)
: FDP cycle (units of the number of lines), 10 bits (write/read)
: FDP1 pulse polarity selection, 1 bits (write/read)
: FDP1 pulse's front edge position, 10 bits (write/read)
: FDP1 pulse's rear edge position, 10 bits (write/read)
: FDP2 pulse polarity selection, 1 bits (write/read)
: FDP2 pulse's front edge position, 10 bits (write/read)
: FDP2 pulse's rear edge position, 10 bits (write/read)
: FDP3 pulse polarity selection, 1 bits (write/read)
: FDP3 pulse's front edge position, 10 bits (write/read)
: FDP3 pulse's rear edge position, 10 bits (write/read)
: Positive pulse AND synthesis between FDP2 and LDP4, 1 bit (write/read)
: Positive pulse OR synthesis between FDP3 and LDP2 bit (write/read)
: Horizontal start position of effective image data, 11 bits (write/read)
: Horizontal end position of effective image data, 11 bits (write/read)
: Vertical start position of effective image data, 10 bits (write/read)
: Vertical end position of effective image data, 10 bits (write/read)
“0”: Synchronizes on the rising edge of CP, “1”: Synchronizes on the falling edge of CP
“0”: Positive pulse, “1”: Negative pulse (same for the following)
“0”: Without synthesis, “1”: With synthesis
“0”: Without synthesis, “1”: With synthesis
PEDL87V3116-02
ML87V3116
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