ml87v2104 Oki Semiconductor, ml87v2104 Datasheet - Page 37

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ml87v2104

Manufacturer Part Number
ml87v2104
Description
Display Controller With Built-in Display Memory And Jpeg
Manufacturer
Oki Semiconductor
Datasheet
2.7 Clock/Power Manager
2.7.1 General Description
OKI Semiconductor
The system clock of the ML87V3116 uses the same pixel clock frequency as display output or a frequency of
x2, x4 or x8. This clock generates the REFCLK input by a built-in PLL using simple integer ratio n/m (n and m
are 1 to 255) as a reference. Power saving can be achieved by setting to a slower system clock frequency at
standby.
The video input clock VCLK and host interface bus clock BCLK are asynchronous with the system clock. The
frequency ratio to the system clock can be set in a range of 1:10 to 10:1.
The system clock is distributed to each function block and its ON/OFF can be controlled individually.
The types of a clock to be distributed are:
• Video input interface
• Display output interface
• JPEG Codec
• Rectangle copy controller
• Data buffer controller and internal SDRAM
• External SDRAM clock for extension data buffers
• I
• Synchronous serial interface (SPI) master
• SD card controller
• Memory stick controller
2
C bus master
PEDL87V3116-02
ML87V3116
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