ml86v7668 Oki Semiconductor, ml86v7668 Datasheet - Page 11

• Manufacturer Part Number: ml86v7668
• Description: Ntsc/pal/secam Digital Video Decoder
• Manufacturer: Oki Semiconductor



Output Block
The output block performs output timing adjustment, picture sizing, output format conversion and other types of
output conversion.
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
Synchronization Block
This block controls the sync signals for internal operation, output sync signals, and the timing for each block.
Synchronization detection levels, output timing, and various other functions can be adjusted by the registers listed
below.

OKI Semiconductor
Digital ACC Function
Hue Adjust Function
Pixel Count Correction Function
Output Format Conversion Function
PLL Function
The digital ACC is the gain adjustment for the chrominance signal output level. Adjustment is automatically
performed by the digital ACC (Auto Chrominance Control), but the adjustment can also be set manually by
using an internal register to set digital MCC (Manual Chrominance Control). In the digital ACC mode, the
burst level is compared with a reference value to determine the amplification rate of the chrominance level. The
default is automatically adjusted to sync level 40IRE, but the level can also be adjusted in an internal register.
Separate U/V level adjustment is also possible.
# Related registers: $40/ACCC, $41/ACCRC
The function for adjusting hue.
Hues can be adjusted by setting the HUE register.
# Related register: $45/HUE
This function uses the internal FIFO to correct the total number of pixels in a line. It corrects the 1-line
sampling error generated when in asynchronous sampling mode or PLL synchronization is lost, and fixes the
pixel count for a line within the active screen. Refer to Active Pixel Timing for more on the pixel count for one
line.
This function converts the output data to the desired output format.
The following output formats are possible.
# Related registers: $00/IOC1, $01/IOC2
The digital PLL circuit generates an operating clock synchronized with the horizontal sync signals of the video
signals. With the input of a 25 MHz or 32 MHz standard clock, the double-speed sampling clock for each mode
is provided as a line lock clock and used as the system clock.
The asynchronous sampling mode, which uses an asynchronous clock directly, can be used without using PLL.
# Related registers: $70/PLLC1, $71/PLLC2, $72/PLLC3, $73/PLLC4
ITU-R BT.656
Y/CbCr
Y/CbCr 16 bits
Y/CbCr 16 bits
RGB
Output mode
(i): interlace
18 bits
8 bits
(i) 4:2:2
(i) 4:2:2
(i) 4:2:2
(i) 4:1:1
(i) 4:4:4
Output Formats
(Pins 30, 31)
IOC2[0] = 0
MODE[3:2]
Control pin
Register
[00]
[01]
[10]
[10]
[11]
IOC2[0] = 1
IOC2[5:4]
Register
Register
[00]
[10]
[10]
[11]
[01]*
Register
IOC2[1]
PEDL86V7668-01
0
0
0
1
0
ML86V7668
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