ml86v7668 Oki Semiconductor, ml86v7668 Datasheet - Page 12

• Manufacturer Part Number: ml86v7668
• Description: Ntsc/pal/secam Digital Video Decoder
• Manufacturer: Oki Semiconductor

VBID Detection Block
This block detects data information and copy protection information from the VBI (Vertical Blanking Interval) of
the input luminance signals. The following four types of VBID data can be detected, and the detection line and
detection level can be changed by altering register settings.
*Note: VBID detection may not provide accurate detection, if the signal status is bad.

OKI Semiconductor
VBID Detection Function
(1) AGC copy protection
Detects whether specified lines include a macrovision AGC pulse (NTSC/PAL) and sets a flag.
# Related registers: $86/AGCD1, $87/AGCD2, $81/VBIDM, $89/AIREG, $92/VFLAG
(2) C. C. (Closed Caption)
Detects whether specified lines include closed caption data (NTSC/PAL), keeps separately the data of even and
odd lines, and sets individual flags.
# Related registers: $82/CCD1, $83/CCD2, $81/VBIDM, $89/AIREG, $92/VFLAG, $93/CCD00,
$94/CCD01, $95/CCDE0, $96/CCDE1
(3) WSS (Wide Screen Signaling)
Detects the WSS data in the lines specified by ETSI (European Telecommunications Standards Institute) and
sets a flag (PAL only).
# Related registers: $88/WSSD, $81/VBIDM, $89/AIREG, $92/VFLAG, $9D/WSSD0, $9E/WSSD1
(4) CGMS (Copy Generation Management System)
Detects the CGMS data in the lines specified by IEC61880 and sets a flag (NTSC only).
# Related registers: $84/CGMS1, $85/CGMS2, $81/VBIDM, $89/AIREG, $92/VFLAG, $97/CGMS00,
$98/CGMS01, $99/CGMS02, $9A/CGMSE0, $9B/CGMSE1, $9C/CGMSE2
In the PLL mode, a double-speed line lock clock is generated by setting the operating mode.
— : Not used
Pin 44 PLLSEL
NTSC Square pixel
PLLSEL = “ 0”
PLLSEL = “ 1”
Operating mode
12.272727 MHz
Fixed clock
Control pin
ITU-R BT.601
PLL clock
13.5 MHz
$70/PLLC1[6] = “ 0” *
Operating Modes/Sampling Clock Settings
*: Default
$01/IOC2[0] = “ 0” *
Sampling clock input according to the
32 MHz
Control pin
MODE[0]
(Pin 33)
(See the table below)
0
1
operating mode
Input Clock Settings
Input clock
$70/PLLC1[6] = “ 1” *
$01/IOC2[0] = “ 1” *
$00/IOC1[1]
25 MHz
Register
0 *
1
Sampling clock (double-speed)
PLL OFF/asynchronous
$70/PLLC1[7] = “ 0” *
$70/PLLC1[7] = “ 1”
PLL ON/line lock
24.545454 MHz
Asynchronous
Pin 46 CLKX2
Sampling
27 MHz
PEDL86V7668-01
ML86V7668
12/31