mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet - Page 10

• Manufacturer Part Number: mt8986al1
• Description: Multiple Rate Digital Switch
• Manufacturer: Zarlink Semiconductor

switch matrices. Usually, different delays occur on the digital backplanes causing the data and frame
synchronization signals to be skewed at the input of the switch device. This may result in the system frame
synchronization pulse to be active at the MT8986 FR input before the first bit of the frame is received at the serial
inputs.
When the input frame offset is enabled, an "internal delay" of up to four clock periods is added to the actual data
input sampling, providing the MT8986 serial timing unit a new input frame reference. An internal virtual frame is
created which is aligned with the framing of the actual serial data coming in at the serial inputs and not with the FR
frame pulse input. In this operation, the transmission of the output frame on the serial links is still aligned to the
frame pulse input signal (FR).
The selection of the data input sampling delay is defined by the CPU in the Frame Input Offset Register (FIO). If this
function is not required in the user's applications, the FIO register should be set up during system initialization to a
state where offset functions are disabled.
Delay Through the MT8986
The switching of information from the input serial streams to the output serial streams results in a delay. Depending
on the type of information to be switched, the MT8986 device can be programmed to perform time-slot interchange
functions with different throughput delay capabilities on a per-channel basis. For voice applications, variable
throughput delay can be selected ensuring minimum delay between input and output data. In wideband data
applications, constant throughput delay can be selected maintaining the frame integrity of the information through
the switch.
The delay through the MT8986 device varies according to the type of throughput delay selected in the V/C bit of the
connect memory high.
Variable Throughput Delay Mode (V/C bit = 0)
Identical I/O Data Rates
The delay in this mode is dependent on the combination of source and destination channels and it is independent of
the input and output streams. The minimum delay achievable in the MT8986 depends on the data rate selected for
the serial streams. For instance, for 2.048 Mb/s the minimum delay achieved corresponds to three time-slots. For
4.096 Mb/s it corresponds to five time-slots while for 8.192 Mb/s it is nine time-slots. Switching configurations with
input and output channels that provides more than its corresponding minimum throughput delay, will have a
throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be
less than one frame period. Table 3a shows the MT8986 throughput delay for each data rate operation.
n= input channel, t.s. = time-slot
Input Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Table 3a - Variable Throughput Delay Values for Identical I/O Rate Applications
128-(n-m) t.s.
32-(n-m) t.s.
64-(n-m) t.s.
m < n
m=n, n+1, n+2
m-n + 128 t.s.
m-n + 32 t.s.
m-n + 64 t.s.
Zarlink Semiconductor Inc.
MT8986
Output Channel (# m)
10
m= n+3, n+4
m-n+128 t.s.
m-n+64 t.s.
m-n t.s.
m=n+5, .. n+8
m-n+128 t.s.
m-n t.s.
m-n t.s.
m > n+8
m-n t.s.
m-n t.s.
m-n t.s.
Data Sheet