mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet - Page 25

• Manufacturer Part Number: mt8986al1
• Description: Multiple Rate Digital Switch
• Manufacturer: Zarlink Semiconductor

MT8986
Data Sheet
Interfacing MT8986 with 8051
The Intel 8051 is a very cost effective solution for many applications that do not require a large CPU interaction and
processing overhead. However, in applications where 8051 is connected to peripherals operating on a synchronous
8 kHz time-base like the MT8986, some connectivity issues have to be addressed. The MT8986 may hold the CPU
read/write cycle due to internal contention between the MT8986 microport and the internal serial to parallel and
parallel to serial converters. Since the 8051 family of CPUs do not provide Data Ready type of inputs, some
external logic and software intervention have to be provided between the MT8986 and the 8051 microcontrollers to
allow read/write operation. The external logic described in Figure 14 is a block diagram of a logical connection
between MT8986 and 8051. Its main function is to store the 8051 data during a write and the MT8986 data during a
read.
For a write, MT8986 address is latched by the internal address latch on the falling edge of the ALE input. Whenever
a read or write operation is done to the MT8986 device, the address decoded signal (MTA) is used to latch or
"freeze" the state of RD, WR, and the ALE signals, until the data acknow-ledge output signal is provided by the
MT8986 device, releasing the latches for a new read/write cycle. Latch U5 is used to hold the 8051 data for a write
until the CPU is ready to accept it (when DTA goes low). Latch U4 stores the MT8986 output data during a read
cycle whenever DTA goes low. When writing to the MT8986, one write operation is sufficient. However, when
reading MT8986, two read operations with the same address are required, with the second being valid.
Enough time need to be provided between two CPU accesses to allow the first access to complete; i.e., to allow for
an internal MT8986 reaction over the first RD/WR access. For a read operation, a minimum of 1220 ns have to be
guaranteed between two successive accesses. For write, at least 800 ns has to be respected.
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