mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet - Page 4

• Manufacturer Part Number: mt8986al1
• Description: Multiple Rate Digital Switch
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
22-29 25-27
33-38 37-39
DIP
19
20
21
30
31
32
39
40
PLCC
29-33
41-43
Pin #
23
24
34
35
36
44
22
44
19-21
23-27
31-33
35-37
QFP
16
17
18
28
29
30
38
44
R/W\WR Read/Write \ Write (Input). In case of non-multiplexed and Motorola multiplexed
STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of
STo6/A6 ST-BUS Output 6/Address 6 input (Three-state output/input). The function of
DS/RD Data Strobe/Read (Input). When non-multiplexed CPU bus or Motorola
STo5-0 ST-BUS Outputs 5 to 0 (Three-state Outputs). Serial data output streams.
Name
AD7-
ODE
AD0
V
CS
SS
multiplexed bus (44 pin only) are selected, this input is DS. This active high input
works in conjunction with CS to enable read and write operation.
For Intel/National multiplexed bus (44 pin only), this input is RD. This active low
input configures the data bus lines (AD0-AD7) as outputs.
buses (44 pin only), this input is R/W. This input controls the direction of the data
bus lines (AD0-AD7) during a microprocessor access.
With Intel/National multiplexed timing (44 pin only), this input is WR. This active
low signal configures the data bus lines (AD0-AD7) as inputs.
Chip Select (Input). Active low input enabling a microprocessor read or write of
the control register or internal memories.
Data Bus (Bidirectional): These pins provide microprocessor access to the
internal control registers, connection memories high and low and data memories.
In multiplexed bus mode (44 pin) these pins also provide the input address to the
internal Address Latch circuit.
Ground.
this pin is determined by the switching configuration enabled. If non-multiplexed
CPU bus is used along with data rates employing 8.192 Mb/s rates, this pin
provides A7 address input function. For 2.048 Mb/s applications or when
multiplexed CPU bus (44 pin only) is selected, this pin assumes STo7 function.
See Tables 1, 2, 6 & 7 for more details.
Note that for applications where A7 input and STo7 output are required
simultaneously (e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should
be connected to pin STi7/A7.
this pin is determined by the switching configuration enabled. If non-multiplexed
CPU bus is used along with a higher data rate employing 8.192 or 4.096 Mb/s,
this pin provides the A6 address input function. For 2.048 Mb/s applications or
when multiplexed CPU bus (44 pin only) is selected, this pin assumes STo6
function. See Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A6 input and STo6 output are required
simultaneously (e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion
applications), the A6 input should be connected to pin STi6/A6.
These serial streams may be composed of 32, 64 and 128 channels at data rates
of 2.048, 4.096 or 8.192 Mbit/s, respectively.
Output Drive Enable (Input). This is the output enable input for the STo0 to
STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input
is high each channel may still be put into high impedance by using per-channel
control bits in Connect Memory High.
Zarlink Semiconductor Inc.
MT8986
4
Description
Data Sheet