mt8977ac Mitel, mt8977ac Datasheet - Page 2

• Manufacturer Part Number: mt8977ac
• Description: Iso-cmos St-bus ?amily T1/esf Framer Circuit
• Manufacturer: Mitel

MT8977
Pin Description
4-100
DIP
10
11
1
2
3
4
5
6
7
8
9
Pin #
TxFDLClk
PLCC
TxFDL
CSTi1
CSTi0
10
13
14
16
11
DSTo
E8Ko
2
3
5
4
9
VSS
RxD
RxA
RxB
TxA
TxB
NC
NC
28 PIN CERDIP/PDIP
TxFDLClk
10
11
12
13
14
1
2
3
4
5
6
7
8
9
TxFDL
Name
CSTi1
DSTo
ISO-CMOS
RxA
RxB
RxD
TxA
TxB
NC
NC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Transmit A Output. Unipolar output that can be used in conjunction with TxB and
external line driver circuitry to generate the bipolar DS1 signal.
Transmit B Output. Unipolar output that can be used in conjunction with TxA
and external line driver circuitry to generate the bipolar DS1 signal.
Data ST-BUS Output. A 2048 kbit/s serial output stream which contains the 24
PCM or data channels received from the DS1 line.
No Connection.
Receive A Complementary Input. Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with
RxB, detects bipolar violations in the received signal.
Receive B Complementary Input.
decoded externally from the received DS1 bipolar signal.
conjunction with RxA, detects bipolar violations in the received signal.
Receive Data Input. Unipolar RZ data signal decoded from the received DS1
signal. Generally the signals input at RxA and RxB are combined externally with a
NAND gate and the resulting composite signal is input at this pin.
Control ST-BUS Input #1.
per-channel control words.
Transmit Facility Data Link (Input). A 4 kHz serial input stream that is
multiplexed into the FDL position in the ESF mode, or the F
96 mode. It is clocked in on the rising edge of TxFDLClk.
Transmit Facility Data Link Clock (Output). A 4 kHz clock used to clock in the
FDL data.
No connection.
VDD
IC
F0i
E1.5i
C1.5i
RxSF
TxSF
C2i
RxFDL
DSTi
RxFDLClk
CSTo
XSt
XCtl
Figure 2 - Pin Connections
TxFDLClk
TxFDL
CSTi1
A 2048 kbit/s serial control stream which carries 24
RxD
RxA
RxB
NC
NC
NC
NC
NC
Description
18 19 20 21 22
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2
Accepts a unipolar split phase signal
44 PIN PLCC
23
1
24 25 26 27 28
44 43 42 41 40
Preliminary Information
S
29
39
38
37
36
35
34
33
32
31
30
pattern when in SLC-
C1.5i
RxSF
TxSF
NC
NC
C2i
NC
NC
NC
NC
RxFDL
This input, in