mt89l86apr1 Zarlink Semiconductor, mt89l86apr1 Datasheet - Page 5

• Manufacturer Part Number: mt89l86apr1
• Description: 512 X 256 Channels 3.3 V Multiple Rate Digital Switch Mrdx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Device Overview
With the integration of voice, video and data services in the same network, there has been an increasing demand
for systems which ensure that data at N x 64 kb/s rates maintain sequence integrity while being transported through
time-slot interchange circuits. This requirement demands time-slot interchange devices which perform switching
with constant throughput delay for wideband data applications while maintaining minimum delay for voice channels.
The MT89L86 device meets the above requirement and allows existing systems based on the MT8980D to be
easily upgraded to maintain the data integrity when wideband data is transported. The device is designed to switch
32, 64 or N x 64 bit/s data. This MT89L86 can provide frame integrity for data applications and minimum throughput
switching delay for voice applications on a per channel basis.
The serial streams of the MT89L86 can operate at 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125 µs wide
frames which contain 32, 64 and 128 channels, respectively. In addition, a built-in rate conversion circuit allows the
user to interconnect various backbone speeds like 2.048 or 4.096 or 8.192 Mb/s while maintaining the control of
throughput delay function on a per-channel basis.
By using Zarlink Message mode capability, the microprocessor can access input and output time-slots on a per
channel basis to control external circuits or other ST-BUS devices. This MT89L86 automatically identifies the
polarity of the frame synchronization input signal and configures its serial port to be compatible to both ST-BUS and
GCI formats.
Two different microprocessor bus interfaces can be selected through an input mode pin (IM): Non-Multiplexed or
Multiplexed. These interfaces provide compatibility with Intel/National multiplexed and Motorola Multiplexed/Non-
Multiplexed buses. The MT89L86 provides a 16 x 8 switching configuration to form a 512 x 256 channel blocking
matrix. Also, a flexible Stream Pair Selection operation allows the software selection of which pair of input and
output streams can be connected to an internal 128 x 128 matrix. See Switching Configurations section for details.
Functional Description
A functional Block Diagram of the 3.3 V MT89L86 is shown in Figure 1. Depending on the application, TDM serial
data can be received at different rates and from different number of serial streams.
Data and Connect Memories
For all data rates, the received serial data is converted to parallel format by the serial to parallel converters and
stored sequentially in a Data Memory. Depending on the selected operation programmed in the IMS (Interface
Mode Select) register, the Data Memory may have up to 512 bytes in use. The sequential addressing of the Data
Memory is performed by an internal counter which is reset by the input 8 kHz frame pulse (FR) marking the frame
boundaries of the incoming serial data streams.
PLCC
44
40
Pin #
SSOP
48
43
STi14/
Name
STo8
ST-BUS Input 14 / ST-BUS Output 8 (Input/three-state output). This pin is only used if
multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is enabled in
the SCB bits (IMS register), this pin is an input that receives serial ST-BUS stream 14 at a data
rate of 2.048 Mbit/s.
If Stream Pair Selection capability is enabled (see switching configuration section), this pin is
the ST-BUS stream 8 output.
When non-multiplexed bus structure is used, this pin should be connected to ground.
Zarlink Semiconductor Inc.
MT89L86
5
Description
Data Sheet