mt89l86apr1 Zarlink Semiconductor, mt89l86apr1 Datasheet - Page 6

• Manufacturer Part Number: mt89l86apr1
• Description: 512 X 256 Channels 3.3 V Multiple Rate Digital Switch Mrdx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

MT89L86
Data Sheet
Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations
in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output
streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be
switched from an ST-BUS input as in connection mode or it can be from the Connect Memory Low as in message
mode. Data destined for a particular channel on the serial output stream is read from the Data Memory or Connect
Memory Low during the previous channel time-slot. This allows enough time for memory access and parallel to
serial conversion.
Connection and Message Modes
In the connection mode, the addresses of the input source data for all output channels are stored in the Connect
memories High (CMH) and Low (CML). The CML and CMH are mapped so that each location corresponds to an
output channel on the output streams. The number of source address bits in CMH and CML to be utilized varies
according to the switching configuration selected in the IMS register. For details on the use of the source address
data (CAB and SAB bits), see CMH and CML bit describe-thin (Figures 5 & 6). Once the source address bits are
programmed by the CPU, the contents of the Data Memory at the selected address are transferred to the parallel-
to-serial converters. By having the output channel specify the source channel through the connect memory, the
user can route the same input channel to several output channels, allowing broadcast facility within the switch.
In the message mode the CPU writes data to the Connect Memory Low locations corresponding to the output link
and channel number. The contents of the Connect Memory Low are transferred directly to the parallel-to-serial
converter one channel before it is to be output. The Connect Memory Low data is transmitted on to the output every
frame until it is changed by the CPU with a new data.
The features of each output channel in the 3.3 V MT89L86 are controlled by the Connect Memory High bits. These
bits determine individual output channels to be in message or connection mode, select throughput delay types and
enable/disable output drivers. The Connect Memory High also provides additional stream and channel address bits
for some configurations. In addition, the Connect Memory High provides one bit to allow the user to control the CST
output in 2.048 Mb/s applications.
If an output channel is set to high-impedance, the TDM serial stream output will be placed in high impedance during
that channel time. In addition to the per-channel control, all channels on the TDM outputs can be placed in high
impedance by pulling the ODE input pin LOW. This overrides the individual per-channel programming by the
Connect Memory High bits.
The Connect Memory data is received via the Microprocessor Interface through the data I/O lines. The addressing
of the MT89L86 internal registers, Data and Connect memories is performed through address input pins and some
bits of the device's Control register. The higher order address bits come from the Control register, which may be
written or read through the microprocessor interface. The lower order address bits come directly from address input
pins. For details on the device addressing, see Software Control and Control register bits description (Figure 3 &
Tables 5, 6 and 7).
Serial Data Interface
The master clock (CLK) can be either at 4.096 or 8.192 MHz allowing serial data link operations at 2.048, 4.096 and
8.192 Mb/s. These data rates can be independently selected on input and output streams allowing this MT89L86
device to be used in various speed backbones and in rate conversion applications. The selected data rates apply to
the inputs or the output streams. Different bit rates among input streams or among output streams are not allowed.
Due to the I/O data rate selection flexibility, two major operations can be selected: Identical or Different I/O data
rates.
The DMO bit (Device Main Operation) in the IMS register is used for selecting between Identical I/O rates or
Different I/O rates. On system power-up, the CPU should set up the DMO, the IDR (Input Data Rate) and ODR
(Output Data Rate) bits located in the IMS register. When Identical I/O data rates are selected by the DMO bit, the
switching configuration and the number of the device's input and output streams can be selected through the SCB
bits (Switching Configuration Bits) in the IMS register. See Switching Configurations section for details.
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