mt9196asr1 Zarlink Semiconductor, mt9196asr1 Datasheet - Page 18

• Manufacturer Part Number: mt9196asr1
• Description: Fully Featured Digital Telephone Circuit With Built-in Filter/codec, Digital Gain Pads, Dtmf Generator, Tone Ringer, And Handset And Speakerphone Transducers
• Manufacturer: Zarlink Semiconductor

MT9196
Data Sheet
perhaps the receive filter is assigned to both the loudspeaker and the Auxiliary Out port. This would allow a voice
recorder or Facsimile machine, connected to the AUXout port to be monitored over the loudspeaker.
The receive filter path itself has two possible signal sources, PCM from the Din port or synthesized tones, from the
digital tone generator. In both cases receive digital gain is assigned automatically. The Receive Path Control
Register combines all of these choices into simple output port assignments.
In ST-BUS mode receive PCM from the Din port must be selected from either the B1 or the B2 channel. Control Bit
B2/B1 in Control Register 1 (address 0Eh) is used to define the active receive B-Channel. In SSI mode the active
PCM channel is automatically defined by the STB input signal.
Sidetone
A voice sidetone path provides proportional transmit signal summing into the receive handset transducer driver.
Details are provided in the Filter/CODEC section.
Watchdog
To maintain program integrity an on-chip watchdog timer is provided for connection to the microcontroller reset pin.
The watchdog output WD goes high while the IDPC is held in reset via PWRST. Release of PWRST will cause WD
to return low immediately and will also start the watchdog timer. The watchdog timer is clocked on the falling edge
of STB/F0i and requires only this input, along with V
, for operation. Note that in SSI mode, if STB disappears the
DD
watchdog will stop clocking. This will not harm processor operation but there is no longer any protection provided.
If the watchdog reset word is written to the watchdog register (address 11h) after PWRST is released, but before
the timeout period (T=512 mSec) expires, a reset of the timer results and WD will remain low. Thereafter, if the reset
word is loaded correctly at intervals less than 'T' then WD will continue low. The first break from this routine, in
which the watchdog register is not written to within the correct interval or it is written to with incorrect data, will result
in a high going WD output after the current interval 'T' expires. WD will then toggle at this rate until the watchdog
register is again written to correctly.
5-Bit Watchdog Reset Word
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
0
1
0
1
0
x=don’t care
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Zarlink Semiconductor Inc.