mt9196asr1 Zarlink Semiconductor, mt9196asr1 Datasheet - Page 40

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mt9196asr1

Manufacturer Part Number
mt9196asr1
Description
Fully Featured Digital Telephone Circuit With Built-in Filter/codec, Digital Gain Pads, Dtmf Generator, Tone Ringer, And Handset And Speakerphone Transducers
Manufacturer
Zarlink Semiconductor
Datasheet
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
AC Electrical Characteristics
1 Bit Cell Period
2 Frame Jitter
3 Bit 1 Dout Delay from STB
4 Bit 2 Dout Delay from STB
5 Bit n Dout Delay from STB
6 Bit 1 Data Boundary
7 Din Bit n Data Setup time from
8 Din Data Hold time from STB
STB
Dout
Din
going high
going high
going high
STB rising
rising
70%
30%
70%
30%
Characteristics
70%
30%
t
dda1
T
t
DATA
su
t
t
ho
dha1
T
/2
t
Bit 1
dda2
DATA1
- SSI BUS Asynchronous Timing (note 1) (see Figure 14)
D1
Figure 14 - SSI Asynchronous Timing Diagram
T
T
DATA
Sym.
T
t
t
t
DATA1
dda1
dda2
ddan
DATA
t
t
T
SU
ho
j
Bit 2
D2
Zarlink Semiconductor Inc.
+500ns+T
+500ns-T
T
T
T
+(n-1) x
+(n-1) x
T
T
(n-1) x
600 +
T
T
600+
DATA
DATA
DATA
Min.
DATA
DATA
T
MT9196
DATA
DATA
DATA
-T
-T
-T
\2
\2
T
40
j
j
j
Bit 3
DATA
j
j
D3
(n-1) x
600 +
Typ.
T
T
7812
3906
600+
DATA
DATA
T
T
T
T
(n-1) x
NOTE: Levels refer to% V
600 +
DATA
600 +
DATA
DATA
Max.
j
600
+600
+T
+T
+T
j
j
j
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCL=128 kHz
BCL=256 kHz
C
C
C
n=3 to 8
n=1-8
L
L
L
=150 pF, R
=150 pF, R
=150 pF, R
Test Conditions
DD
(CMOS I/O)
Data Sheet
T
j
L
L
L
=1K
=1K
=1K

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